ST72F621L4M1 STMicroelectronics, ST72F621L4M1 Datasheet - Page 73

• Manufacturer Part Number: ST72F621L4M1
• Description: IC MCU 8BIT LS 16K 34-SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F621L4M1

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 34-SOIC (7.5mm Width)
• Processor Series: ST72F6x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI, SPI, USB
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 2
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit
• For Use With: 497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: In Transition
• Other names: 497-2112-5

SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Framing Error
A framing error is detected when:
– The stop bit is not recognized on reception at the
– A break is received.
When the framing error is detected:
– the FE bit is set by hardware
– Data is transferred from the Shift register to the
– No interrupt is generated. However this bit rises
The FE bit is reset by a SCISR register read oper-
ation followed by a SCIDR register read operation.
10.5.4.4 Conventional Baud Rate Generation
The baud rate for the receiver and transmitter (Rx
and Tx) are set independently and calculated as
follows:
with:
PR = 1, 3, 4 or 13 (see SCP[1:0] bits)
TR = 1, 2, 4, 8, 16, 32, 64,128
(see SCT[2:0] bits)
RR = 1, 2, 4, 8, 16, 32, 64,128
(see SCR[2:0] bits)
All these bits are in the SCIBRR register.
Example: If f
PR = 13 and TR = RR = 1, the transmit and re-
ceive baud rates are 38400 baud.
Note: The baud rate registers MUST NOT be
changed while the transmitter or the receiver is en-
abled.
10.5.4.5 Extended Baud Rate Generation
The extended prescaler option gives a very fine
tuning on the baud rate, using a 255 value prescal-
er, whereas the conventional Baud Rate Genera-
tor retains industry standard software compatibili-
ty.
The extended baud rate generator block diagram
is described in the
The output clock rate sent to the transmitter or to
the receiver is the output from the 16 divider divid-
ed by a factor ranging from 1 to 255 set in the SCI-
ERPR or the SCIETPR register.
expected time, following either a de-synchroni-
zation or excessive noise.
SCIDR register.
at the same time as the RDRF bit which itself
generates an interrupt.
Tx =
(16
f
CPU
*
PR)
CPU
*
TR
is 8 MHz (normal mode) and if
Figure 48
Rx =
(16
f
CPU
*
PR)
*
RR
Doc ID 6996 Rev 5
Note: the extended prescaler is activated by set-
ting the SCIETPR or SCIERPR register to a value
other than zero. The baud rates are calculated as
follows:
with:
ETPR = 1,..,255 (see SCIETPR register)
ERPR = 1,.. 255 (see SCIERPR register)
10.5.4.6 Receiver Muting and Wake-up Feature
In multiprocessor configurations it is often desira-
ble that only the intended message recipient
should actively receive the full message contents,
thus reducing redundant SCI service overhead for
all non addressed receivers.
The non addressed devices may be placed in
sleep mode by means of the muting function.
Setting the RWU bit by software puts the SCI in
sleep mode:
All the reception status bits can not be set.
All the receive interrupts are inhibited.
A muted receiver may be awakened by one of the
following two ways:
– by Idle Line detection if the WAKE bit is reset,
– by Address Mark detection if the WAKE bit is set.
Receiver wakes-up by Idle Line detection when
the Receive line has recognized an Idle Frame.
Then the RWU bit is reset by hardware but the
IDLE bit is not set.
Receiver wakes-up by Address Mark detection
when it received a “1” as the most significant bit of
a word, thus indicating that the message is an ad-
dress. The reception of this particular word wakes
up the receiver, resets the RWU bit and sets the
RDRF bit, which allows the receiver to receive this
word normally and to use it as an address word.
CAUTION: In Mute mode, do not write to the
SCICR2 register. If the SCI is in Mute mode during
the read operation (RWU = 1) and a address mark
wake up event occurs (RWU is reset) before the
write operation, the RWU bit is set again by this
write operation. Consequently the address byte is
lost and the SCI is not woken up from Mute mode.
Tx =
16
*
ETPR*(PR*TR)
f
CPU
Rx =
16
*
ERPR*(PR*RR)
f
CPU
ST7262xxx
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