PIC17LC756A-08/L Microchip Technology, PIC17LC756A-08/L Datasheet - Page 150

• Manufacturer Part Number: PIC17LC756A-08/L
• Description: IC MCU OTP 16KX16 A/D 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17LC756A-08/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• Processor Series: PIC17LC
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 902 B
• Interface Type: I2C, MSSP, RS- 232, SCI, SPI, USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 8
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 12 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC17C7XX
15.2.3
While in SLEEP mode, the I
addresses or data and when an address match or com-
plete byte transfer occurs, wake the processor from
SLEEP (if the SSP interrupt is enabled).
TABLE 15-3:
DS30289B-page 150
07h, Unbanked INTSTA
10h, Bank 4
11h, Bank 4
10h. Bank 6
14h, Bank 6
11h, Bank 6
12h, Bank 6
13h, Bank 6
Legend:
Address
x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the SSP in I
SLEEP OPERATION
PIR2
PIE2
SSPADD
SSPBUF
SSPCON1
SSPCON2
SSPSTAT
Name
REGISTERS ASSOCIATED WITH I
Synchronous Serial Port (I
Synchronous Serial Port Receive Buffer/Transmit Register
SSPIE
WCOL
SSPIF
GCEN
Bit 7
PEIF
SMP
2
C module can receive
ACKSTAT
T0CKIF
SSPOV
BCLIF
BCLIE
Bit 6
CKE
SSPEN
ACKDT
ADIE
Bit 5
ADIF
T0IF
D/A
2
C mode) Address Register
ACKEN
INTF
Bit 4
CKP
—
—
P
2
C OPERATION
SSPM3
CA4IF
CA4IE
RCEN
PEIE
Bit 3
S
15.2.4
A RESET disables the SSP module and terminates the
current transfer.
T0CKIE
SSPM2
CA3IF
CA3IE
Bit 2
PEN
R/W
EFFECTS OF A RESET
SSPM1
TX2IE
RSEN
TX2IF
Bit 1
T0IE
UA
SSPM0
RC2IE
RC2IF
INTE
Bit 0
SEN
BF
2000 Microchip Technology Inc.
2
C mode.
0000 0000
000- 0000
000- 0000
0000 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
POR, BOR
MCLR, WDT
0000 0000
000- 0000
000- 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000