PIC18F4431-I/ML Microchip Technology, PIC18F4431-I/ML Datasheet
PIC18F4431-I/ML
Specifications of PIC18F4431-I/ML
Related parts for PIC18F4431-I/ML
PIC18F4431-I/ML Summary of contents
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... PIC18F2331/2431/4331/4431 Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D © 2007 Microchip Technology Inc. Data Sheet 28/40/44-Pin Enhanced Flash Preliminary DS39616C ...
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... PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... PIC18F2431 16384 8192 768 PIC18F4331 8192 4096 768 PIC18F4431 16384 8192 768 © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Power-Managed Modes: • Run: CPU on, Peripherals on • Idle: CPU off, Peripherals on • Sleep: CPU off, Peripherals off • Idle mode Currents Down to 5.8 μA, Typical • ...
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... RA4/AN4/CAP3/QEB OSC2/CLKO/RA6 Note 1: Low-Voltage Programming must be enabled. DS39616C-page -/CAP1/INDX 1 21 REF +/CAP2/QEA 2 20 REF 3 19 PIC18F2331 PIC18F2431 OSC1/CLKI/RA7 Preliminary RB7/KBI3/PGD RB6/KBI2/PGC (1) RB5/KBI1/PWM4/PGM RB4/KBI0/PWM5 RB3/PWM3 RB2/PWM2 RB1/PWM1 RB0/PWM0 RC7/RX/DT/SDO RC6/TX/CK/SS RC5/INT2/SCK/SCL RC4/INT1/SDI/SDA RB3/PWM3 RB2/PWM2 RB1/PWM1 RB0/PWM0 RC7/RX/DT/SDO © 2007 Microchip Technology Inc. ...
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... Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin for SCK/SCL. 2: Low-Voltage Programming must be enabled. 3: RD4 is the alternate pin for FLTA. 4: RD5 is the alternate pin for PWM4. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 ...
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... Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin for SCK/SCL. 2: Low-Voltage Programming must be enabled. 3: RD4 is the alternate pin for FLTA. 4: RD5 is the alternate pin for PWM4. DS39616C-page RC0/T1OSO/T1CKI OSC2/CLKO/RA6 3 30 OSC1/CLKI/RA7 4 PIC18F4331 PIC18F4431 27 RE2/AN8 7 RE1/AN7 8 26 RE0/AN6 9 25 RA5/AN5/LVDIN RA4/AN4/CAP3/QEB 11 Preliminary SS DD © 2007 Microchip Technology Inc. ...
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... Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin for SCK/SCL. 2: Low-Voltage Programming must be enabled. 3: RD4 is the alternate pin for FLTA. 4: RD5 is the alternate pin for PWM4. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 OSC2/CLKO/RA6 1 33 OSC1/CLKI/RA7 PIC18F4331 PIC18F4431 7 27 RE2/AN8 8 RE1/AN7 26 9 RE0/AN6 25 RA5/AN5/LVDIN RA4/AN4/CAP3/QEB Preliminary SS DD DS39616C-page 5 ...
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... Appendix E: Migration From Mid-Range to Enhanced Devices ......................................................................................................... 383 Appendix F: Migration From High-End to Enhanced Devices............................................................................................................ 383 Index .................................................................................................................................................................................................. 385 The Microchip Web Site ..................................................................................................................................................................... 395 Customer Change Notification Service .............................................................................................................................................. 395 Customer Support .............................................................................................................................................................................. 395 Reader Response .............................................................................................................................................................................. 396 Product Identification System............................................................................................................................................................. 397 DS39616C-page 6 Preliminary © 2007 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Preliminary DS39616C-page 7 ...
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... PIC18F2331/2431/4331/4431 NOTES: DS39616C-page 8 Preliminary © 2007 Microchip Technology Inc. ...
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... This document contains device specific information for the following devices: • PIC18F2331 • PIC18F4331 • PIC18F2431 • PIC18F4431 This family offers the advantages of all PIC18 microcontrollers – namely, high computational perfor- mance at an economical price, with the addition of high endurance enhanced Flash program memory and a high-speed 10-bit A/D Converter ...
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... Timer5 as the time base, a Special Event Trigger to other modules and an adjustable noise filter on each IC input. • Extended Watchdog Timer (WDT): This enhanced version incorporates a 16-bit prescaler, allowing a time-out range from over 2 minutes, that is stable across operating voltage and temperature. Preliminary © 2007 Microchip Technology Inc. ...
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... SPDIP 28-pin SPDIP 28-pin SOIC 28-pin SOIC 28-pin QFN 28-pin QFN Preliminary program memory (8 Kbytes for devices, 16 Kbytes for 5 bidirectional ports on PIC18F4331 PIC18F4431 DC – 40 MHz DC – 40 MHz 8192 16384 4096 8192 768 768 256 256 34 34 Ports Ports Channels) (8 Channels) ...
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... RA2/AN2/V -/CAP1/INDX REF RA3/AN3/V +/CAP2/QEA REF RA4/AN4/CAP3/QEB OSC2/CLKO/RA6 OSC1/CLKI/RA7 PORTB RB0/PWM0 RB1/PWM1 RB2/PWM2 RB3/PWM3 RB4/KBI0/PWM5 RB5/KBI1/PWM4/PGM RB6/KBI2/PGC RB7/KBI3/PGD PORTC RC0/T1OSO/T1CKI RC1/T1OSI/CCP2/FLTA RC2/CCP1/FLTB RC3/T0CKI/T5CKI/INT0 RC4/INT1/SDI/SDA RC5/INT2/SCK/SCL RC6/TX/CK/SS RC7/RX/DT/SDO 8 PORTE (1,2) MCLR/V /RE3 PP HS 10-Bit ADC PCPWM MFM © 2007 Microchip Technology Inc. ...
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... RE3 is available only when MCLR is disabled. 2: RD4 is the alternate pin for FLTA. 3: RC3, RC4 and RC5 are alternate pins for T0CKI/T5CKI, SDI/SDA, SCK/SCL, respectively. 4: RD5 is the alternate pin for PWM4. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Data Bus<8> Data Latch 8 8 Data RAM ...
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... A/D reference voltage (high) input Input capture pin Quadrature Encoder Interface channel A input pin. 3 I/O TTL Digital I/O. I Analog Analog input Input capture pin Quadrature Encoder Interface channel B input pin. CMOS = CMOS compatible input or output I = Input P = Power ) DD Preliminary Description © 2007 Microchip Technology Inc. ...
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... KBI3 PGD Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output OD = Open-Drain (no diode to V © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Pin Buffer Type Type QFN PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. ...
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... EUSART synchronous data (see related TX/CK). O — SPI data out — Ground reference for logic and I/O pins — Positive supply for logic and I/O pins. CMOS = CMOS compatible input or output I = Input P = Power ) DD Preliminary Description 2 C mode. © 2007 Microchip Technology Inc. ...
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... Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin for SCK/SCL. 2: RD4 is the alternate pin for FLTA. 3: RD5 is the alternate pin for PWM4. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Pin Buffer Type Type 18 Master Clear (input) or programming voltage (input) ...
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... TTL Digital I/O. I Analog Analog input Input capture pin Quadrature Encoder Interface channel B input pin. 24 I/O TTL Digital I/O. I Analog Analog input 5. I Analog Low-Voltage Detect input. CMOS = CMOS compatible input or output I = Input P = Power ) DD Preliminary Description © 2007 Microchip Technology Inc. ...
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... RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin for SCK/SCL. 2: RD4 is the alternate pin for FLTA. 3: RD5 is the alternate pin for PWM4. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Pin Buffer Type Type PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs ...
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... EUSART synchronous clock (see related RX/DT SPI slave select input. 1 I/O ST Digital I/ EUSART asynchronous receive. I/O ST EUSART synchronous data (see related TX/CK). O — SPI data out. CMOS = CMOS compatible input or output I = Input P = Power ) DD Preliminary Description 2 C mode. © 2007 Microchip Technology Inc. ...
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... RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin for SCK/SCL. 2: RD4 is the alternate pin for FLTA. 3: RD5 is the alternate pin for PWM4. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Pin Buffer Type Type PORTD is a bidirectional I/O port. ...
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... Analog input 7. 27 I/O ST Digital I/O. I Analog Analog input 8. P — Ground reference for logic and I/O pins — Positive supply for logic and I/O pins connect. CMOS = CMOS compatible input or output I = Input P = Power ) DD Preliminary Description © 2007 Microchip Technology Inc. ...
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... The oscillator design requires the use of a parallel cut crystal. Note: Use of a series cut crystal may give a frequency out of manufacturers’ specifications. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 2-1: (1) C1 (1) C2 Note 1: See Table 2-1 and Table 2-2 for initial values of C1 and C2 ...
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... DD OSC2 HS Mode Crystal OSC1 Osc of external Preliminary EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION) OSC1 PIC18FXXXX (HS Mode) OSC2 Open PLL BLOCK DIAGRAM HS Osc Enable PLL Enable Phase F IN Comparator F OUT Loop Filter ÷4 VCO SYSCLK © 2007 Microchip Technology Inc. ...
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... CONFIGURATION) OSC1/CLKI Clock from Ext. System PIC18FXXXX RA6 I/O (OSC2) © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 2.5 RC Oscillator For timing insensitive applications, the RC and RCIO device options offer additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (R ...
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... Code execution continues during this shift. There is no indication that the shift has occurred. Oper- ation of features that depend on the INTRC clock source frequency, such as the WDT, Fail-Safe Clock Monitor and peripherals, will also be affected by the change in frequency. /4, OSC Preliminary © 2007 Microchip Technology Inc. ...
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... Center frequency. Oscillator module is running at the calibrated frequency. 111111 • • • • 100000 = Minimum frequency © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 R/W-0 R/W-0 R/W-0 TUN4 TUN3 TUN2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
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... SLEEP instruction will be ignored recommended that the Timer1 oscillator be operating and stable before executing the SLEEP instruction very long delay may occur while the Timer1 oscillator starts. Preliminary © 2007 Microchip Technology Inc. ...
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... Sleep OSC1 Secondary Oscillator T1OSO T1OSCEN Enable Oscillator T1OSI OSCCON<6:4> Internal Oscillator Block INTRC Source © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 PIC18F2331/2431/4331/4431 CONFIG1H <3:0> HSPLL 4 x PLL LP, XT, HS, RC, EC Clock Source Option for other Modules OSCCON<6:4> 8 MHz 111 4 MHz 110 2 MHz ...
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... Primary oscillator (Sleep and PRI_IDLE modes) Note 1: Depends on the state of the IESO bit in Configuration Register 1H. DS39616C-page 30 (1) R/W-0 R R-0 IRCF0 OSTS IOFS U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 SCS1 SCS0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... EC LP, XT and HS Note: See Table 4-1 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 If the Sleep mode is selected, all clock sources are stopped. Since all the transistor switching currents have been stopped, Sleep mode achieves the lowest current consumption of the device (only leakage currents) ...
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... PIC18F2331/2431/4331/4431 NOTES: DS39616C-page 32 Preliminary © 2007 Microchip Technology Inc. ...
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... RC_IDLE 1 1x Note 1: Includes INTOSC and INTOSC postscaler, as well as the INTRC source. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 For PIC18F2331/2431/4331/4431 devices, the power- managed modes are invoked by using the existing SLEEP instruction. All modes exit to PRI_RUN mode when triggered by an interrupt, a Reset or a WDT time- out (PRI_RUN mode is the normal full power execution mode ...
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... Figure 3-2 shows how the system is clocked during the clock source switch. The example assumes the device was in SEC_IDLE or SEC_RUN mode when a wake is triggered (the primary clock was configured in HSPLL mode). Preliminary © 2007 Microchip Technology Inc. is less than 3V specifications are violated. ...
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... SLEEP instruction. This is both the Reset state of the OSCCON register and the setting that selects Sleep mode. This maintains compatibility with other PIC devices that do not offer power-managed modes. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 WDT Time-out Peripherals are Causes a ... ...
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... TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL) OSC1 (1) T OST PLL Clock Output CPU Clock Peripheral Clock Program PC Counter Wake Event Note 1024 (approx). These intervals are not shown to scale. OST OSC PLL DS39616C-page (1) T PLL OSTS bit Set Preliminary © 2007 Microchip Technology Inc. ...
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... Clock Program PC Counter Wake Event © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 When a wake event occurs, the CPU is clocked from the primary clock source. A delay of approximately 10 μs is required between the wake event and when code execution starts. This is required to allow the CPU to become ready to execute instructions ...
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... T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the system clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run Clock Transition (1) T PLL Clock Transition OSTS bit Set Preliminary © 2007 Microchip Technology Inc. ...
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... These intervals are not shown to scale. OST OSC PLL © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 instruction was executed, and the INTOSC source was already stable, the IOFS bit will remain set. If the IRCF bits are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear ...
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... Figure 3-6). When the clock switch is complete, the Timer1 oscillator is disabled, the T1RUN bit is cleared, the OSTS bit is set and the primary clock provides the system clock. The IDLEN and SCS bits are not affected by the wake-up Clock Transition Preliminary © 2007 Microchip Technology Inc. ...
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... INTRC OSC1 CPU Clock Peripheral Clock Program PC Counter © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Note: Caution should be used when modifying a single IRCF bit possible to select a higher clock speed than is supported by the low V Improper device operation may result if the V If the IRCF bits are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear ...
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... On all exits from Low-Power mode by interrupt, code execution branches to the interrupt vector if the GIE/GIEH bit (INTCON<7>) is set. Otherwise, code execution continues or resumes without branching (see Section 9.0 “Interrupts”). Preliminary © 2007 Microchip Technology Inc. ...
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... Execution continues during the INTOSC stabilization period. 5: Required delay when waking from Sleep and all Idle modes. This delay runs concurrently with any other required delays (see Section 3.3 “Idle Modes”). © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Clock Ready Status bit ...
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... INTRC clock source is selected. Being able to adjust the INTOSC requires knowing when an adjustment is required, in which direction it should be made, and in some cases, how large a change is needed. Three examples follow, but other techniques may be used. Preliminary © 2007 Microchip Technology Inc. ...
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... If the internally clocked timer value is greater than expected, then the internal oscillator block is running too fast – decrement OSCTUNE. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 3.6.3 EXAMPLE A CCP module can use free-running Timer1, clocked by the internal oscillator block and an external event with a known period (i ...
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... PIC18F2331/2431/4331/4431 NOTES: DS39616C-page 46 Preliminary © 2007 Microchip Technology Inc. ...
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... Ripple Counter Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin. 2: See Table 4-1 for time-out situations. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation ...
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... PWRT. Preliminary ) is typically PLL falls below V (parameter D005A BOR (parameter 35), BOR falls below V for less than T . BOR BOR rises DD rises above then will keep BOR PWRT drops below V while the DD BOR rises above V , the Power-up DD BOR © 2007 Microchip Technology Inc. ...
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... Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (0x000008h or 0x000018h). © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, all time-outs will expire. Bring- ing MCLR high will begin execution immediately (Figure 4-5) ...
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... --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu (1) uuuu uuuu (1) uuuu -u-u (1) uu-u u-uu N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu uuuu uuuu N/A N/A N/A N/A N/A © 2007 Microchip Technology Inc. ...
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... Bit 3 of PORTE and LATE are enabled if MCLR functionality is disabled. When not enabled as the PORTE pin, they are disabled and read as ‘0’. The 28-pin devices have only RE3 on PORTE when MCLR is disabled. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 MCLR Resets ...
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... Microchip Technology Inc. ...
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... Bit 3 of PORTE and LATE are enabled if MCLR functionality is disabled. When not enabled as the PORTE pin, they are disabled and read as ‘0’. The 28-pin devices have only RE3 on PORTE when MCLR is disabled. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 MCLR Resets ...
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... Microchip Technology Inc. ...
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... Bit 3 of PORTE and LATE are enabled if MCLR functionality is disabled. When not enabled as the PORTE pin, they are disabled and read as ‘0’. The 28-pin devices have only RE3 on PORTE when MCLR is disabled. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 MCLR Resets ...
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... PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET DS39616C-page 56 T PWRT T OST T PWRT T OST T PWRT T OST Preliminary © 2007 Microchip Technology Inc RISE < PWRT ): CASE CASE 2 DD ...
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... TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. OST ≈ max. First three stages of the PWRT timer. T PLL © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 , V RISE > PWRT T OST T PWRT T ...
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... PIC18F2331/2431/4331/4431 NOTES: DS39616C-page 58 Preliminary © 2007 Microchip Technology Inc. ...
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... High-Priority Interrupt Vector LSb Low-Priority Interrupt Vector LSb On-Chip Flash Program Memory Unused Read ‘0’s © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 5.1 Program Memory Organization A 21-bit program counter is capable of addressing the 2-Mbyte program memory space. Accessing a location between the physically implemented memory and the 2-Mbyte address will cause a read of all ‘ ...
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... This is not the same as a Reset as the contents of the SFRs are not affected. Return Address Stack 11111 11110 11101 STKPTR<4:0> TOSL 34h 00011 001A34h Top-of-Stack 00010 000D58h 00001 00000 Preliminary 00010 © 2007 Microchip Technology Inc. ...
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... POP instruction. The POP instruc- tion discards the current TOS by decrementing the Stack Pointer. The previous value pushed onto the stack then becomes the TOS value. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 R/W-0 R/W-0 R/W-0 ...
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... The PC increments address sequential instructions in the program memory. The CALL, RCALL, instructions write to the program counter directly. For these instructions, the contents of PCLATH and PCLATU are not transferred to the program counter. Preliminary © 2007 Microchip Technology Inc. GOTO and program branch ...
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... Instruction @ address SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 5.6 Instruction Flow/Pipelining An “ ...
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... Execute this word as a NOP REG3 ; continue code REG1 ; is RAM location 0? REG1, REG2 ; Yes, execute this word ; 2nd word of instruction REG3 ; continue code Preliminary Word Address ↓ 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h © 2007 Microchip Technology Inc. ...
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... The table read/table write operation is discussed further in Section 6.1 “Table Reads and Table Writes”. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 5.9 Data Memory Organization The data memory is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory ...
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... The BSR is ignored and the Access Bank is used. The first 96 bytes are General Purpose RAM (from Bank 0). The second 160 bytes are Special Function Registers (from Bank 15). When The BSR specifies the bank used by the instruction. © 2007 Microchip Technology Inc. ...
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... FC1h ADCON1 FE0h BSR FC0h ADCON2 © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 “core” are described in this section, while those related to the operation of the peripheral features are described in the section of that peripheral feature. The SFRs are typically distributed among the peripherals whose functions they control. ...
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... N/A 51, 73 N/A 51, 73 N/A 51, 73 N/A 51, 73 N/A 51, 73 51, 73 ---- 0000 51, 73 xxxx xxxx DC C ---x xxxx 51, 75 51, 137 0000 0000 51, 137 xxxx xxxx T0PS1 T0PS0 51, 135 1111 1111 © 2007 Microchip Technology Inc. ...
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... These registers and/or bits are not implemented on the PIC18F2331/2431 devices and read as ‘0’. 6: The RE3 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’; otherwise, RE3 reads ‘0’. This bit is read-only. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Bit 4 ...
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... RE0 53, 133 ---- xxxx RD0 xxxx xxxx 53, 130 RC0 53, 125 xxxx xxxx RB0 53, 119 xxxx xxxx RA0 53, 113 xx0x 0000 PTMOD0 54, 186 0000 0000 — 00-- ---- 54, 186 184 0000 0000 184 ---- 0000 184 1111 1111 184 ---- 1111 © 2007 Microchip Technology Inc. ...
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... These registers and/or bits are not implemented on the PIC18F2331/2431 devices and read as ‘0’. 6: The RE3 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’; otherwise, RE3 reads ‘0’. This bit is read-only. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Bit 4 ...
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... Registers” provides a description of Indirect Address- ing, which allows linear addressing of the entire RAM space. Direct Addressing (3) From Opcode 7 0 (3) 00h 01h 000h 100h Data (1) Memory 0FFh 1FFh Bank 0 Bank 1 Preliminary 0Eh 0Fh E00h F00h EFFh FFFh Bank 14 Bank 15 © 2007 Microchip Technology Inc. ...
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... FSR1H:FSR1L. INDFn can be used in code anywhere an operand can be used. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 If INDF0, INDF1 or INDF2 are read indirectly via a FSRn, all ‘0’s are read (Zero bit is set). Similarly, if INDF0, INDF1 or INDF2 are written to indirectly, the operation will be equivalent to a NOP instruction and the Status bits are not affected ...
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... INDIRECT ADDRESSING 3 11 Note 1: For register file map detail, see Table 5-1. DS39616C-page 74 0h RAM Address FFFh 12 File Address = access of an Indirect Addressing register File FSRn Indirect Addressing FSRnH:FSRnL Location Select 0000h Data (1) Memory 0FFFh Preliminary © 2007 Microchip Technology Inc. ...
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... For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 For example, CLRF STATUS will clear the upper three bits and set the Z bit ...
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... It is recommended that the POR bit be set after a Power-on Reset has been detected, so that subsequent Power-on Resets may be detected. R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 POR BOR bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer points to a byte in program memory. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The program memory space is 16 bits wide, while the data RAM space is 8 bits wide. Table reads and table writes move data between these two memory spaces DD through an 8-bit register (TABLAT) ...
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... See Section 6.3 “Reading the Flash Program Memory” regarding table reads. Note: Interrupt flag bit, EEIF in the PIR2 register, is set when the write is complete. It must be cleared in software. Preliminary © 2007 Microchip Technology Inc. Table Latch (8-bit) TABLAT ...
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... RD is cleared in hardware. The RD bit can only be set (not cleared) in soft- ware. RD bit cannot be set when EEPGD = 1 Read completed Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 R/W-0 R/W-x R/W-0 (1) ...
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... TBLPTR based on Flash program memory operations. Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 LONG WRITE – TBLPTR<21:3> READ or WRITE – TBLPTR<21:0> Preliminary TBLPTRL 0 © 2007 Microchip Technology Inc. ...
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... TBLRD*+ MOVFW TABLAT MOVWF WORD_ODD © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 6-4 shows the interface between the internal program memory and the TABLAT ...
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... Execute a NOP. 9. Re-enable interrupts. ; load TBLPTR with the base ; address of the memory block ; point to Flash program memory ; enable write to memory ; enable Row Erase operation ; disable interrupts ; write 55H ; write 0AAH ; start erase (CPU stall) ; re-enable interrupts Preliminary © 2007 Microchip Technology Inc. ...
Page 85
... CFGS bit to access program memory; - set WREN bit to enable byte writes. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Since the Table Latch (TABLAT) is only a single byte, the TBLWT instruction has to be executed 8 times for each programming operation. All of the table write operations will essentially be short writes, because only the holding registers are written ...
Page 86
... FSR0 ; present data to table latch ; short write ; to internal TBLWT holding register, increment ; TBLPTR ; loop until buffers are full Preliminary © 2007 Microchip Technology Inc. ...
Page 87
... Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 ; disable interrupts ; required sequence ; write 55H ...
Page 88
... PIC18F2331/2431/4331/4431 NOTES: DS39616C-page 86 Preliminary © 2007 Microchip Technology Inc. ...
Page 89
... EECON2 is not a physical register. Reading EECON2 will read all ‘0’s. The EECON2 register is used exclusively in the memory write and erase sequences. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Control bit, EEPGD, determines if the access will be to program or data EEPROM memory. When clear, oper- ations will access the data EEPROM memory ...
Page 90
... When a WRERR occurs, the EEPGD and FREE bits are not cleared. This allows tracing of the error condition. DS39616C-page 88 R/W-0 R/W-x R/W-0 (1) FREE WRERR WREN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/S-0 R/S bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 91
... BSF INTCON, GIE SLEEP BCF EECON1, WREN © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 After a write sequence has been initiated, EECON1, EEADR and EEDATA cannot be modified. The WR bit will be inhibited from being set unless the WREN bit is set. The WREN bit must be set on a previous instruc- tion ...
Page 92
... RBIF 0000 000x 0000 000u 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 RD xx-0 x000 uu-0 u000 CCP2IP 1--1 -1-1 1--1 -1-1 CCP2IF 0--0 -0-0 0--0 -0-0 CCP2IE 0--0 -0-0 0--0 -0-0 © 2007 Microchip Technology Inc. ...
Page 93
... Hardware Multiply Without Hardware Multiply Unsigned Hardware Multiply Without Hardware Multiply Signed Hardware Multiply © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 8.2 Operation Example 8-1 shows the sequence unsigned multiply. Only one instruction is required when one argument of the multiply is already loaded in the WREG register. ...
Page 94
... ARG2H, W SUBWFB RES3 ; CONT_CODE : Preliminary SIGNED MULTIPLICATION ALGORITHM SIGNED MULTIPLY ROUTINE ; ARG1L * ARG2L -> ; PRODH:PRODL ; ; ; ARG1H * ARG2H -> ; PRODH:PRODL ; ; ; ARG1L * ARG2H -> ; PRODH:PRODL ; ; Add cross ; products ; ; ; ; ; ARG1H * ARG2L -> ; PRODH:PRODL ; ; Add cross ; products ; ; ; ; ARG2H:ARG2L neg? ; no, check ARG1 ; ; ; ; ARG1H:ARG1L neg? ; no, done ; ; ; © 2007 Microchip Technology Inc. ...
Page 95
... Individual interrupts can be disabled through their corresponding enable bits. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are devices ...
Page 96
... INT2IE INT2IP IPEN IPEN PEIE/GIEL IPEN TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP Preliminary © 2007 Microchip Technology Inc. Wake- Power-Managed Mode Interrupt to CPU Vector to Location 0008h GIE/GIEH Interrupt to CPU Vector to Location 0018h PEIE/GIEL ...
Page 97
... None of the RB7:RB4 pins have changed state Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Note: Interrupt flag bits are set when an interrupt ...
Page 98
... User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS39616C-page 96 R/W-1 U-0 R/W-1 INTEDG2 — TMR0IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 R/W-1 — RBIP bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 99
... Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 R/W-0 ...
Page 100
... R-0 R/W-0 R/W-0 TXIF SSPIF CCP1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 101
... A TMR1 register capture occurred (must be cleared in software TMR1 register capture occurred Compare mode TMR1 register compare match occurred (must be cleared in software TMR1 register compare match occurred PWM mode: Not used in this mode. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 R/W-0 U-0 R/W-0 EEIF — ...
Page 102
... Timer5 time base matched the PR5 value (must be cleared in software Timer5 time base did not match the PR5 value DS39616C-page 100 R/W-0 R/W-0 R/W-0 PTIF IC3DRIF IC2QEIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 IC1IF TMR5IF bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 103
... TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 R/W-0 R/W-0 R/W-0 TXIE SSPIE CCP1IE U = Unimplemented bit, read as ‘ ...
Page 104
... Unimplemented: Read as ‘0’ bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled DS39616C-page 102 R/W-0 U-0 R/W-0 EEIE — LVDIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 R/W-0 — CCP2IE bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 105
... IC1IE: IC1 Interrupt Enable bit 1 = IC1 interrupt enabled 0 = IC1 interrupt disabled bit 0 TMR5IE: Timer5 Interrupt Enable bit 1 = Timer5 interrupt enabled 0 = Timer5 interrupt disabled © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 R/W-0 R/W-0 R/W-0 PTIE IC3DRIE IC2QEIE U = Unimplemented bit, read as ‘0’ ...
Page 106
... TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority DS39616C-page 104 R/W-1 R/W-1 R/W-1 TXIP SSPIP CCPIP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 107
... LVDIP: Low-Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 Unimplemented: Read as ‘0’ bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 R/W-1 U-0 R/W-1 EEIP — LVDIP U = Unimplemented bit, read as ‘0’ ...
Page 108
... Low priority bit 0 TMR5IP: Timer5 Interrupt Priority bit 1 = High priority 0 = Low priority DS39616C-page 106 R/W-1 R/W-1 R/W-1 PTIP IC3DRIP IC2QEIP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 IC1IP TMR5IP bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 109
... For details of bit operation, see Register 5-3. bit 1 POR: Power-on Reset Status bit For details of bit operation, see Register 5-3. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 5-3. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 R/W-1 R-1 R Unimplemented bit, read as ‘ ...
Page 110
... Example 9-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. ; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR_TMEP located anywhere ; Restore BSR ; Restore WREG ; Restore STATUS Preliminary © 2007 Microchip Technology Inc. ...
Page 111
... PORT Note 1: I/O pins have diode protection to V © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 10.1 PORTA, TRISA and LATA Registers PORTA is an 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i ...
Page 112
... Data Latch D N I/O Pin WR TRISA V TRIS Latch SS RD TRISA TTL Input Buffer RD PORTA To A/D Converter Analog Input Mode Preliminary BLOCK DIAGRAM OF RA1 LATA Q RA1 Analog Input Mode TTL I/O Pin Schmitt Trigger TTL Input Buffer © 2007 Microchip Technology Inc. ...
Page 113
... FIGURE 10-5: BLOCK DIAGRAM OF RA4 Data Bus D WR LATA or PORTA Data Latch D WR TRISA TRIS Latch RD PORTA To A/D Converter To CAP3/QEB Note 1: Open-drain usually available on RA4 has been removed for this device. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 RD LATA Analog Input Mode ...
Page 114
... PORTA I/O Pin TTL Input Buffer RD PORTA To Oscillator I/O Pin V SS TTL Input Buffer D EN Preliminary BLOCK DIAGRAM OF RA7 INTOSC Enable To Oscillator RD LATA Data Latch N I/O Pin TRIS Latch INTOSC w/RA7 Enable TTL Input RD TRISA Buffer © 2007 Microchip Technology Inc. ...
Page 115
... RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. 2: ANS5 through ANS8 are available only on the PIC18F4331/4431 devices. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Buffer TTL Input/output or analog input. ...
Page 116
... RB<0:3> and RB4 pins are multiplexed with the 14-bit PWM module for PWM<0:3> and PWM5 output. The RB5 pin can be configured by the Configuration bit PWM4MX as the alternate pin for PWM4 output. Preliminary © 2007 Microchip Technology Inc. ...
Page 117
... RBPU PORT/PWM Select PWM0 Data RD LATB Data Bus D WR LATB or PORTB CK Data Latch D WR TRISB CK TRIS Latch RD TRISB RD PORTB Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 ...
Page 118
... RD PORTB Set RBIF From other RB7:RB4 pins Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). DS39616C-page 116 PORTB EN Q3 Preliminary V DD Weak P Pull-up RB4 Pin TTL Input Buffer © 2007 Microchip Technology Inc. ...
Page 119
... PORT/PWM Select PWM4 Data Data Bus PORTB CK Q Data Latch TRISB CK TRIS Latch RD TRISB RD PORTB Set RBIF From other RB7:RB4 pins LVP Configuration Bit Low-Voltage Programming Enable 0 = Only High-Voltage Programming © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 RBPU TTL Input Buffer PORTB EN Q3 Enable ICSP™ ...
Page 120
... Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). 2: PGC is available on RB6. 3: PGD is available on RB7. DS39616C-page 118 ( Enable Q Debug RBx Enable Debug Q TRISBx Q TTL Input Buffer PORTB EN Q3 Preliminary V DD Weak P Pull-up RB7/RB6 Pin Schmitt Trigger © 2007 Microchip Technology Inc. ...
Page 121
... INTCON3 INT2IP INT1IP — Legend unknown unchanged value depends on condition unimplemented, read as ‘0’. Shaded cells are not used by PORTB. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Function (1) Input/output pin or PCPWM output PWM0. Internal software programmable weak pull-up. (1) Input/output pin or PCPWM output PWM1. Internal software programmable weak pull-up ...
Page 122
... CLRF LATC ; Alternate method ; to clear output ; data latches MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISC ; Set RC<3:0> as inputs ; RC<5:4> as outputs ; RC<7:6> as inputs Schmitt Trigger Preliminary © 2007 Microchip Technology Inc. RC0 Pin Timer1 Oscillator To RC1 Pin ...
Page 123
... Note 1: FLTA input is multiplexed with RC1 and RD4 using FLTAMX Configuration bit in CONFIG3H register. FIGURE 10-15: BLOCK DIAGRAM OF RC2 PORT/CCP1 Select CCP1 Data Out RD LATC Data Bus D WR LATC or PORTC CK Data Latch D WR TRISC CK TRIS Latch RD TRISC RD PORTC CCP1 Input/FLTB Input © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 ...
Page 124
... RD TRISC SDA Drive RD PORTC SDI/SDA Input Note 1: The SDI/SDA bits are multiplexed with RD2 and RC4 pins by the SSPMX bit in the Configuration register. DS39616C-page 122 Schmitt Trigger Schmitt Trigger Preliminary RC3 Pin (1) EXCLKMX_enable RC4 Pin (1) SSPMX © 2007 Microchip Technology Inc. ...
Page 125
... Note 1: SCK/SCL are multiplexed on RD3 and RC5 using SSPMX bit in the Configuration register. FIGURE 10-19: BLOCK DIAGRAM OF RC6 EUSART Select TX Data Out/CK RD LATC Data Bus D WR LATC or PORTC CK Data Latch D WR TRISC CK TRIS Latch RD TRISC EUSART Select RD PORTC CK Input SS Input © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Schmitt Trigger ...
Page 126
... RD TRISC (1) EUSART Select RD PORTC RX/DT Data Input Note 1: EUSART is in Synchronous Master Transmission mode only (SYNC = 2: SDO must have its TRISC bit cleared in order to be able to drive RC7. DS39616C-page 124 Preliminary RC7 Pin Schmitt Trigger TXEN = ). © 2007 Microchip Technology Inc. ...
Page 127
... INTEDG0 INTEDG1 INTEDG2 INTCON3 INT2IP INT1IP — Legend unknown unchanged unimplemented, read as ‘0’. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 ST Input/output port pin or Timer1 oscillator output/Timer1 clock input. Compare2 output/PWM output when CCP2Mx bit is disabled or FLTA input. ST Input/output port pin, Capture1 input/Compare1 output/PWM1 output or FLTB input ...
Page 128
... PORTD ; Initialize PORTD by ; clearing output ; data latches CLRF LATD ; Alternate method ; to clear output ; data latches MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISD ; Set RD<3:0> as inputs ; RD<5:4> as outputs ; RD<7:6> as inputs Schmitt Trigger Preliminary © 2007 Microchip Technology Inc. RD<7:6> Pin ...
Page 129
... CK TRIS Latch RD TRISD RD PORTD FIGURE 10-23: BLOCK DIAGRAM OF RD4 RD LATD Data Bus LATD or PORTD CK Q Data Latch TRISD CK Q TRIS Latch RD TRISD RD PORTD FLTA Input Note 1: FLTAMX is located in the Configuration register, CONFIG3H. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Schmitt Trigger Schmitt ...
Page 130
... TRIS Latch RD TRISD SDA Drive RD PORTD SDI/SDA Input Note 1: The SDI/SDA bits are multiplexed on RD2 and RC4 pins by the SSPMX bit in the Configuration register. DS39616C-page 128 Schmitt Trigger Preliminary RD3 Pin (1) SSPMX RD2 Pin (1) Schmitt SSPMX Trigger © 2007 Microchip Technology Inc. ...
Page 131
... Note 1: The SDO output is multiplexed by the SSPMX bit in the Configuration register. FIGURE 10-27: BLOCK DIAGRAM OF RD0 RD LATD Data Bus D WR LATD or PORTD CK Data Latch D WR TRISD CK TRIS Latch RD TRISD RD PORTD T0CKI/T5CKI Input Note 1: T0CKI/T5CKI are multiplexed by the SSPMX bit in the Configuration register. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 ...
Page 132
... Input/output port pin or PCPWM output PWM7. Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RD4 RD3 RD2 RD1 RD0 Preliminary Value on Value on all other POR, BOR Resets xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 1111 1111 1111 1111 © 2007 Microchip Technology Inc. ...
Page 133
... The Data Latch register (LATE) is also memory mapped. Read-modify-write operations on the LATE register read and write the latched output value for PORTE. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The fourth pin of PORTE (MCLR/V only pin. Its operation is controlled by the MCLRE Configuration bit (CONFIG3H< ...
Page 134
... MCLRE Data Bus RD TRISE Schmitt Trigger RD LATE Latch PORTE High-Voltage Detect MCLRE Internal MCLR FILTER Note 1: Pin requires special protection due to HV. DS39616C-page 132 Analog Input Mode (1) /RE3 HV Low-Level MCLR Detect Preliminary RE<2:0> Pins Schmitt Trigger © 2007 Microchip Technology Inc. ...
Page 135
... Shaded cells are not used by PORTE. Note 1: Implemented only when Master Clear functionality is disabled (CONFIG3H<7> = 0). 2: ANS5 through ANS8 are available only on PIC18F4331/4431 devices. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 U-0 U-0 R/W-1 — ...
Page 136
... PIC18F2331/2431/4331/4431 NOTES: DS39616C-page 134 Preliminary © 2007 Microchip Technology Inc. ...
Page 137
... Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Figure 11-1 shows a simplified block diagram of the Timer0 module in 8-bit mode and Figure 11-2 shows a simplified block diagram of the Timer0 module in 16-bit mode. ...
Page 138
... T0PS2, T0PS1, T0PS0 1 Sync with Internal TMR0L Clocks Delay PSA Preliminary Data Bus 8 TMR0 Set Interrupt Flag bit TMR0IF on Overflow Set Interrupt TMR0 Flag bit TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 Data Bus<7:0> © 2007 Microchip Technology Inc. ...
Page 139
... TRISA6 PORTA Data Direction Register Legend unknown unchanged. Shaded cells are not used by Timer0. Note 1: RA6 and RA7 are enabled as I/O pins depending on the oscillator mode selected in Configuration Word 1H. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 11.2.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software con- trol (i.e., it can be changed “ ...
Page 140
... PIC18F2331/2431/4331/4431 NOTES: DS39616C-page 138 Preliminary © 2007 Microchip Technology Inc. ...
Page 141
... OSC bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Register 12-1 details the Timer1 Control register. This register controls the operating mode of the Timer1 module and contains the Timer1 Oscillator Enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit, TMR1ON (T1CON< ...
Page 142
... CCP Special Event Trigger CLR TMR1L TMR1ON On/Off 1 T1OSCEN F /4 OSC Enable Internal 0 (1) Oscillator Clock TMR1CS T1CKPS1:T1CKPS0 Preliminary become inputs. That is, the Synchronized 0 Clock Input 1 Synchronize det 2 Peripheral Clocks Synchronized 0 Clock Input 1 T1SYNC Synchronize Prescaler det 2 Peripheral Clocks © 2007 Microchip Technology Inc. ...
Page 143
... Capacitor values are for design guidance only. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 12.3 Timer1 Oscillator Layout Considerations The Timer1 oscillator for PIC18F2331/2431/4331/4431 devices incorporates an additional low-power feature. When this option is selected, it allows the oscillator to automatically reduce its power consumption when the microcontroller is in Sleep mode ...
Page 144
... For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. Preliminary © 2007 Microchip Technology Inc. ...
Page 145
... T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 u0uu uuuu Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ...
Page 146
... PIC18F2331/2431/4331/4431 NOTES: DS39616C-page 144 Preliminary © 2007 Microchip Technology Inc. ...
Page 147
... Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 13.1 Timer2 Operation Timer2 can be used as the PWM time base for the PWM mode of the CCP module. The TMR2 register is readable and writable and is cleared on any device Reset ...
Page 148
... Value on Value on Bit 0 all other POR, BOR Resets RBIF 0000 000x 0000 000u TMR1IF -000 0000 -000 0000 TMR1IE -000 0000 -000 0000 TMR1IP -111 1111 -111 1111 0000 0000 0000 0000 1111 1111 1111 1111 © 2007 Microchip Technology Inc. ...
Page 149
... These bits are not implemented on PIC18F2331/2431 devices and read as ‘0’. 2: For Timer5 to operate during Sleep mode, T5SYNC must be set. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Timer5 is a general purpose timer/counter that incor- porates additional features for use with the Motion Feedback Module (see Section 16.0 “ ...
Page 150
... Timer5 prescaler divides the input not at all (1:1). The TMR5 register pair increments on Q1. Clearing TMR5CS (= 0) selects the internal device clock as the timer sampling clock. Preliminary 1 Internal Data Bus 0 Timer5 On/Off Write TMR5L Read TMR5L 8 8 © 2007 Microchip Technology Inc. ...
Page 151
... Timer5 is disabled and a Special Event Trigger Reset is present on the Timer5 Reset input. (See Section 14.7 “Timer5 Special Event Trigger Reset Input” for additional information). © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 14.2 16-Bit Read/Write and Write Modes As noted, the actual high byte of the Timer5 register pair is mapped to TMR5H, which serves as a buffer ...
Page 152
... TMR5CS • T5SYNC 14.8.1 INTERRUPT DETECT IN SLEEP MODE When configured as described above, Timer5 will continue to increment on each rising edge on T5CKI while in Sleep mode. When a TMR5/PR5 match occurs, an interrupt is generated which can wake the part. Preliminary © 2007 Microchip Technology Inc. ...
Page 153
... T5SEN RESEN T5MOD CAP1CON — CAP1REN — DFLTCON — FLT4EN FLT3EN Legend unknown unchanged unimplemented. Shaded cells are not used by the Timer5 module. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Bit 4 Bit 3 Bit 2 Bit 1 INT0IE RBIE TMR0IF INT0IF PTIP IC3DRIP IC2QEIP IC1IP ...
Page 154
... PIC18F2331/2431/4331/4431 NOTES: DS39616C-page 152 Preliminary © 2007 Microchip Technology Inc. ...
Page 155
... Compare mode; initialize CCPx pin high; on compare match, force CCPx pin low (CCPxIF bit is set) 1010 = Compare mode; generate software interrupt on compare match (CCPxIF bit is set, CCPx pin is unaffected) 1011 = Compare mode; Special Event Trigger (CCPxIF bit is set) 11xx = PWM mode © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 15-1: CCP Mode Capture ...
Page 156
... Set Flag bit CCP2IF CCPR2H Prescaler TMR1 Enable and TMR1H CCP2CON<3:0> Preliminary CHANGING BETWEEN CAPTURE PRESCALERS ; Turn CCP module off ; Load WREG with the ; new prescaler mode ; value and CCP ON ; Load CCP1CON with ; this value CCPR1L TMR1L CCPR2L TMR1L © 2007 Microchip Technology Inc. ...
Page 157
... RC2/CCP1 Pin TRISC<2> Output Enable Q RC1/CCP2 Pin TRISC<1> Output Enable © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 15.4.2 TIMER1 MODE SELECTION Timer1 must be running in Timer mode or Synchro- nized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. ...
Page 158
... CCP2IF 0--0 -0-0 0--0 -0-0 CCP2IE 0--0 -0-0 0--0 -0-0 CCP2IP 1--1 -1-1 1--1 -1-1 © 2007 Microchip Technology Inc. ...
Page 159
... FIGURE 15-4: PWM OUTPUT Period Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2 © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 15.5.1 PWM PERIOD The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following equation: EQUATION 15-1: PWM Period = [(PR2 • ...
Page 160
... TMR1IP -111 1111 -111 1111 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP1M0 --00 0000 --00 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP2M0 --00 0000 --00 0000 © 2007 Microchip Technology Inc. ...
Page 161
... Counter Overflow Flag for Low Rotation Speed • Utilizes Input Capture 1 Logic (IC1) • High and Low Velocity Support © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Many of the features for the IC and QEI submodules are fully programmable, creating a flexible peripheral structure that can accommodate a wide range of in-system uses ...
Page 162
... Direction QEA Clock QEI Control Logic CHGIF INDX QEI Logic IC3DRIF IC3IF QEI Mode Decoder QEIF IC2QEIF IC2IF Preliminary TMR5IF Special Event Trigger Output TMR5<15:0> 8 IC3IF 8 IC2IF 8 IC1IF Special Event Trigger Reset Position Counter QEIF 8 8 © 2007 Microchip Technology Inc. ...
Page 163
... Q Clocks Note 1: CAP1BUF register is reconfigured as VELR register when QEI mode is active. 2: QEI generated velocity pulses, vel_out, are downsampled to produce this velocity capture signal. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Input Channel 1 (IC1) includes a Special Event Trigger that can be configured for use in Velocity Mea- surement mode ...
Page 164
... CAP3BUF is enabled as MAXCNT when QEI mode is active. DS39616C-page 162 and Mode Select (1) Q Clocks (1) ICxIF Capture Clock/ (1) CAPxBUF_clk Reset/ Interrupt Decode Logic Reset (1) CAPxM<3:0> Preliminary Capture Clock (1,2,3) CAPxBUF TMR5 Enable TMR5 TMR5 Reset Timer Reset Control (2) CAPxREN © 2007 Microchip Technology Inc. ...
Page 165
... Capture mode, every rising edge 0001 = Capture mode, every falling edge 0000 = Input Capture x (ICx) off Note 1: Special Event Trigger is only available on CAP1. For CAP2 and CAP3, this configuration is unused. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Note: Throughout this section, references to registers, ...
Page 166
... BCF CAP1CON, CAP1REN . In the event that a write to TMR5 coincides with an input capture event, CY clock edge when the capture event takes place (see Note CY Preliminary 0002 0000 0001 0002 0003 0002 Note 5 © 2007 Microchip Technology Inc. ...
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... Pulse-Width Measurement mode active on each rising edge detected. In the falling to rising Pulse-Width Measurement mode active on each falling edge detected. 5: TMR5 Reset pulse is activated on the capture edge. CAP1REN bit has no bearing in this mode. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Timer5 is always reset on the edge when the measurement is first initiated ...
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... Timer5 reset and the interrupt generated. Any change on CAP1, CAP2 or CAP3 is detected and the associated time base count is captured. For position and velocity measurement in this mode, the timer can be optionally reset (see Section 16.1.6 “Timer5 Reset” for Reset options Preliminary © 2007 Microchip Technology Inc. ...
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... With the Special Event Trigger Reset disabled, Timer5 cannot be reset by the Special Event Trigger Reset on the CAP1 input. In order for the Special Event Trigger Reset to work as the Reset trigger to Timer5, IC1 must be configured in the Special Event Trigger mode (CAP1M<3:0> = 1110 or 1111). © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 16.1.6 ...
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... Captures Timer5 on pulse boundaries. (1) TMR5 optional Captures Timer5 on state change. (1) TMR5 optional Simple Edge Capture mode (includes a selectable prescaler). (1) TMR5 optional Captures Timer5 on period boundaries. TMR5 always Captures Timer5 on pulse boundaries. (1) TMR5 optional Captures Timer5 on state change. Preliminary Description © 2007 Microchip Technology Inc. ...
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... CAP3/QEB Filter CAP2/QEA Filter CAP1/INDX © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The QEI control logic detects the leading edge on the QEA or QEB phase input pins and generates the count pulse, which is sent to the position counter logic. It also samples the index input signal (INDX) and generates the direction of the rotation signal (up/down) and the velocity event signals ...
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... QEI will take precedence and IC will remain disabled. R/W-0 R/W-0 R/W-0 (2,3) (2,3) (2,3) QEIM2 QEIM1 QEIM0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (4) (2,3) Preliminary R/W-0 R/W-0 PDEC1 PDEC0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... QEA and QEB edge. Like QEI x2 mode, the position counter can be reset by an input on the pin (QEIM2:QEIM0 = 101 the period match event (QEIM2:QEIM0 = 010). © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 16.2.3 QEI OPERATION The Position Counter register pair (POSCNTH: ...
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... Update mode 1024) with F to 2.5 MHz, which corresponds to F Figure 16-9 shows QEA and QEB quadrature input timing when sampled by the noise filter. Preliminary directly proportional to POS = 4D • RPM POS MIPS is equal CY of 625 kHz. QEI © 2007 Microchip Technology Inc. ...
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... POSCNT = 0 (when decrementing), which occurs on the next QEA falling edge. 3: IC2QEIF is generated on Q4 rising edge. 4: Position counter is loaded with ‘0’ (which is a rollover event in this case) on POSCNT = MAXCNT. 5: Position counter is loaded with MAXCNT value (1527h) on underflow. 6: IC2QEIF must be cleared in software. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 ( ...
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... Position counter is loaded with MAXCNT value (e.g., 1527h) on the next QEA or QEB edge following the INDX falling edge input signal detect). 6: IC2QEIF must be cleared in software. DS39616C-page 174 Reverse Note Note 6 (3) (3) Q4 (5) ( ’ on the next QEA or QEB edge. POSCNT is set to clock cycle. CY Preliminary © 2007 Microchip Technology Inc. ...
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... Velocity Event CAP3/QEB QEB QEA CAP2/QEA INDX CAP1/INDX © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 16.2.6.1 Velocity Event Timing The event pulses are reduced by a fixed ratio by the velocity pulse divider. The divider is useful for high-speed measurements where the velocity events happen frequently. By producing a single output pulse for a given number of input event pulses, the counter can track larger pulse counts (i ...
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... CAP1REN bit (CAP1CON<6>). When CAP1REN is cleared, the TMR5 time base will not be reset on any velocity event capture pulse. The VELR register pair, however, will continue to be updated with the current TMR5 value. Preliminary Q1 © 2007 Microchip Technology Inc. ...
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... Note 1: Noise filter output enables are functional in both QEI and IC Operating modes. Note: The Noise Filter is intended for random high-frequency filtering and not continuous high-frequency filtering. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 programmed by the FLTCK2:FLTCK0 Configuration bits used as the clock reference to the clock CY divider block ...
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... If the CAPx interrupt is enabled, the device will wake-up from Sleep. This effectively enables all input a velocity capture channels to be used as the external interrupts. 16.5.2 QEI IN SLEEP MODE All QEI functions are halted in Sleep mode. Update Preliminary QEI CY (3) Noise Glitch © 2007 Microchip Technology Inc. ...
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... Shaded cells are not used by the Motion Feedback Module. Note 1: Register name and function determined by which submodule is selected (IC/QEI, respectively). See Section 16.1.10 “Other Operating Modes” for more information. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Bit 4 Bit 3 Bit 2 ...
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... PIC18F2331/2431/4331/4431 NOTES: DS39616C-page 180 Preliminary © 2007 Microchip Technology Inc. ...
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... Switched Reluctance Motors • Brushless DC (BLDC) Motors • Uninterruptible Power Supplies (UPS) • Multiple DC Brush Motors © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The PWM module has the following features: • eight PWM I/O pins with four duty cycle generators. Pins can be paired to get a complete half-bridge control ...
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... Channel 1 Generator 1 Dead-Time Generator and Override Logic PWM Channel 0 Generator 0 Dead-Time Generator and Override Logic Special Event Special Event Trigger Postscaler Preliminary (2) PWM7 (2) (2) PWM6 PWM5 Output PWM4 Driver Block PWM3 PWM2 PWM1 PWM0 FLTA (2) FLTB © 2007 Microchip Technology Inc. ...
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... In Complementary modes, the even PWM pins must always be the complement of the corresponding odd PWM pin. For example, PWM0 will be the complement of PWM1, PWM2 will be the complement of PWM3 and so on. The dead-time © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 V DD Dead-Band ...
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... The PWM time base is configured through the PTCON0 and PTCON1 registers. The time base is enabled or disabled by respectively setting or clearing the PTEN bit in the PTCON1 register. Note: The PTMR register pair (PTMRL:PTMRH) is not cleared when the PTEN bit is cleared in software. Preliminary © 2007 Microchip Technology Inc. ...
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... The PWM time base can be configured for four different modes of operation: • Free-Running mode • Single-Shot mode • Continuous Up/Down Count mode • Continuous Up/Down Count mode with interrupts for double updates © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 PTMR Clock Timer Reset Up/Down Zero Match Timer ...
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... OSC /256 (1:64 prescale) OSC U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 PTMOD1 PTMOD0 bit Bit is unknown U-0 U-0 — — bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... PWM<7:0> outputs are enabled for PIC18F4331/4431 devices. When PWMEN2:PWMEN0 = 111, PWM outputs 1, 3 and 5 are enabled in PIC18F2331/2431 devices; PWM outputs and 7 are enabled in PIC18F4331/4431 devices. 3: Unimplemented in PIC18F2331/2431 devices; maintain these bits clear. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 (1) R/W-1 R/W-0 R/W-0 ...
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... Write to the PTMR register • Write to the PTCON (PTCON0 or PTCON1) register • Any device Reset Note: The PTMR register is not cleared when PTCONx is written. timer counts Preliminary U-0 R/W-0 R/W-0 — UDIS OSYNC bit Bit is unknown /4) has prescaler OSC © 2007 Microchip Technology Inc. ...
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... Qc Qc PTMR FFEh PTMR_INT_REQ PTIF bit Note 1: PWM Time Base Period register, PTPER, is loaded with the value FFFh for this example. © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 17.3.5 PWM TIME BASE POSTSCALER The match output of PTMR can optionally MHz postscaled through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate an interrupt ...
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... The postscaler selection bits may be used in this mode of the timer to reduce the frequency of the interrupt events. Figure 17-7 shows the interrupts in Continuous Up/Down Count mode FFFh 000h FFFh 000h 1 Preliminary Up/Down Count mode 000h 000h 000h 000h © 2007 Microchip Technology Inc. ...
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... PWM TIME BASE INTERRUPT, CONTINUOUS UP/DOWN COUNT MODE A: PRESCALER = 1 OSC PTMR 002h PTDIR bit PTMR_INT_REQ 1 1 PTIF bit B: PRESCALER = 1 002h PTMR PTDIR bit 1 1 PTMR_INT_REQ PTIF bit Note 1: Interrupt flag bit, PTIF, is sampled here (every Q1). © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 001h 000h 001h 000h 1 1 Preliminary Q2 Q3 ...
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... Do not change PTMOD while PTEN is active. It will yield unexpected results. To change the PWM Timer mode of opera- tion, first clear PTEN bit, load PTMOD with required data and then set PTEN 3FEh 3FFh 001h 000h 1 1 Preliminary 3FEh 3FDh 001h 002h © 2007 Microchip Technology Inc. ...
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... The PWM frequency is the inverse of period; or: EQUATION 17-3: PWM FREQUENCY 1 PWM Frequency = PWM Period © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The maximum resolution (in bits) for a given device oscillator and PWM frequency can be determined from the following formula: EQUATION 17-4: Resolution = The PWM resolutions and frequencies are shown for a selection of execution speeds and PTPER values in Table 17-2 ...
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... PWM PERIOD BUFFER UPDATES IN CONTINUOUS UP/DOWN COUNT MODE New PTPER Value = 007 Old PTPER Value = 004 1 0 DS39616C-page 194 Period Value Loaded from PTPER Register New Value Written to PTPER Register Period Value Loaded from PTPER Register New Value Written to PTPER Register Preliminary © 2007 Microchip Technology Inc. ...
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... duty cycle match occurs duty cycle match occurs duty cycle match occurs on Q4 © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The value in each Duty Cycle register determines the amount of time that the PWM output is in the active state. The upper 12 bits of PDCx holds the actual duty cycle value from PTMRH/L< ...
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... PTPER register. FIGURE 17-12: PTPER PTMR PDCx Value (old) PDCx (new) 0 Duty Cycle Active at beginning of period Duty Cycle Value Loaded from Buffer Register New Value Written to Duty Cycle Buffer Preliminary EDGE-ALIGNED PWM New Duty Cycle Latched Period © 2007 Microchip Technology Inc. ...
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... Duty Cycle Start of first PWM period © 2007 Microchip Technology Inc. PIC18F2331/2431/4331/4431 New Values Written to Duty Cycle Buffer inactive for the entire PWM period. In addition, the output on the PWM pin will be active for the entire PWM period if the value in the Duty Cycle register is equal to or greater than the value in the PTPER register ...
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... OUTPUTS +V The Complementary mode is selected for each PWM I/O pin pair by clearing the appropriate PMODx bit in the PWMCON0 register. The PWM I/O pins are set to Complementary mode by default upon all kinds of device Resets. Preliminary © 2007 Microchip Technology Inc. 3-Phase Load ...