DSPIC30F5013-20E/PT Microchip Technology, DSPIC30F5013-20E/PT Datasheet - Page 20

• Manufacturer Part Number: DSPIC30F5013-20E/PT
• Description: IC DSPIC MCU/DSP 66K 80TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F5013-20E/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 66KB (22K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-TFQFP
• For Use With: DM300024 - KIT DEMO DSPICDEM 1.1XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPDM300004-2 - BOARD DEMO DSPICDEM.NET 2DM300004-1 - BOARD DEMO DSPICDEM.NET 1AC30F007 - MODULE SKT FOR DSPIC30F 80TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DSPIC30F5013-20EP

dsPIC30F Family Reference Manual
35.3.4
35.3.5
DS70272B-page 35-20
SPI1 Receive-only Operation
SPI1 Error Handling
Setting the DISSDO control bit (SPI1CON1<11>) disables transmission at the SDO1 pin. This
allows the SPI1 module to be configured for a Receive-only mode of operation. The SDO1 pin
will be controlled by the respective port function if the DISSDO bit is set.
The DISSDO function is applicable to all SPI operating modes.
If a new data word has been shifted into SPI1SR but the previous SPI1BUF contents have not
been read, the SPIROV bit (SPI1STAT<6>) will be set. Any received data in SPI1SR will not be
transferred, and further data reception is disabled until the SPIROV bit is cleared. The SPIROV
bit is not cleared automatically by the module; it must be cleared by the user application.
The SPI1 Interrupt Flag, SPI1IF, is set whenever the SPIROV, SPIRBF (SPI1STAT<0>) or
SPITBF (SPI1STAT<1>) bits are set. The interrupt flag cannot be cleared by hardware and must
be reset in software. The actual SPI1 interrupt is generated only when the corresponding SPI1IE
bit is set in the IEC0 Control register.
© 2008 Microchip Technology Inc.