ATMEGA32U4-MU Atmel, ATMEGA32U4-MU Datasheet - Page 86

• Manufacturer Part Number: ATMEGA32U4-MU
• Description: MCU AVR 32K FLASH 16MHZ 44-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32U4-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-VQFN
• Package: 44QFN EP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 26
• Interface Type: EBI/I2S/SPI/TWI/USART/USB
• On-chip Adc: 12-chx10-bit
• Number Of Timers: 5
• For Use With: ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATMEGA32U4-16MU; ATMEGA32U4-16MU

11.0.2
7766F–AVR–11/10
External Interrupt Control Register B – EICRB
Table 11-1.
Note:
Table 11-2.
• Bit 7..6 – Res: Reserved Bits
These bits are reserved bits in the ATmega16U4/ATmega32U4 and always read as zero.
• Bits 5, 4 – ISC61, ISC60: External Interrupt 6 Sense Control Bits
The External Interrupt 6 is activated by the external pin INT6 if the SREG I-flag and the corre-
sponding interrupt mask in the EIMSK is set. The level and edges on the external pin that
activate the interrupt are defined in
detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock
period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt.
Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider is
enabled. If low level interrupt is selected, the low level must be held until the completion of the
currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will
generate an interrupt request as long as the pin is held low.
Table 11-3.
Note:
Bit
Read/Write
Initial Value
Symbol
ISCn1
ISC61
t
0
0
1
1
0
0
1
1
INT
1. n = 3, 2, 1or 0.
1. When changing the ISC61/ISC60 bits, the interrupt must be disabled by clearing its Interrupt
ISC60
ISCn0
When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt
Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.
Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.
Parameter
Minimum pulse width for
asynchronous external interrupt
0
1
0
1
0
1
0
1
7
-
R/W
0
Asynchronous External Interrupt Characteristics
Interrupt Sense Control
Interrupt Sense Control
Description
The low level of INT6 generates an interrupt request.
Any logical change on INT6 generates an interrupt request
The falling edge between two samples of INT6 generates an interrupt
request.
The rising edge between two samples of INT6 generates an interrupt
request.
Description
The low level of INTn generates an interrupt request.
Any edge of INTn generates asynchronously an interrupt request.
The falling edge of INTn generates asynchronously an interrupt request.
The rising edge of INTn generates asynchronously an interrupt request.
6
-
R/W
0
5
ISC61
R/W
0
Table
4
ISC60
R/W
0
(1)
(1)
11-3. The value on the INT6 pin are sampled before
3
-
0
R/W
Condition
2
-
R/W
0
Min
1
-
R/W
0
ATmega16/32U4
Typ
50
0
-
R/W
0
Max
EICRB
Units
ns
86