PIC18F8390-I/PT Microchip Technology, PIC18F8390-I/PT Datasheet - Page 8

• Manufacturer Part Number: PIC18F8390-I/PT
• Description: IC PIC MCU FLASH 4KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F8390-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 80-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, LCD, POR, PWM, WDT
• Number Of I /o: 66
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SPI, I2C, EUSART, AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 66
• Number Of Timers: 4
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163028
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPDM163028 - BOARD DEMO PICDEM LCDAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F6390/6490/8390/8490
17. Module: EUSART
18. Module: EUSART
19. Module: EUSART
20. Module: MSSP
DS80207F-page 8
The EUSART auto-baud feature may periodically
measure the incoming baud rate incorrectly. The
rate of incorrect baud rate measurements will
depend on the frequency of the incoming
synchronization byte and the system clock
frequency.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
In Synchronous mode (SYNC = 1) with clock
polarity high (SCKP = 1), the EUSART transmits a
shorter than expected clock on the CKx pin for bit
0.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
In Synchronous mode, EUSART baud rates using
SPBRGx values of ‘0’ and ‘1’ may not function
correctly.
Work around
Use another baud rate configuration to generate
the desired baud rate.
Date Codes that pertain to this issue:
All engineering and production devices.
In an I
unaddressed slave may respond to bus activity
when data on the bus matches its address. The
first occurrence will set the BF bit. The second
occurrence will set the BF and SSPOV bits. In both
situations, the SSPIF bit is not set and an interrupt
will not occur. The device will vector to the Interrupt
Service Routine only if the interrupt is enabled and
an address match occurs.
Work around
The I
I
Date Codes that pertain to this issue:
All engineering and production devices.
2
C address match to maintain normal operation.
2
C slave must clear the SSPOV bit after each
2
C™ system with multiple slave nodes, an
21. Module: MSSP
22. Module: MSSP
23. Module: MSSP
In I
work correctly.
Work around
Use a BRG value greater than ‘0’ by setting
SSPADD ≥ 1.
Date Codes that pertain to this issue:
All engineering and production devices.
In I
ware to begin data reception and cleared by the
peripheral after a byte is received. After a byte is
received, the device may take up to 80 T
RCEN and 800 T
and MPLAB ICE emulators.
Work around
Single byte receptions are typically not affected,
since the delay between byte receptions is
typically long enough for the RCEN bit to clear. For
multiple byte receptions, the software must wait
until the bit is cleared by the peripheral before the
next byte can be received.
Date Codes that pertain to this issue:
All engineering and production devices.
Setting the SEN bit initiates a Start sequence on
the bus, after which, the SEN bit is cleared auto-
matically by hardware. If the SEN bit is set again
(without an address byte being transmitted), a
Start sequence will not commence and the SEN bit
will not be cleared. This condition causes the bus
to remain in an active state. The system is Idle
when ACKEN, RCEN, PEN, RSEN and SEN are
clear.
Work around
Set the PEN or RSEN bit to transmit a Stop or
Repeated Start sequence, although the SEN bit
may still be set, indicating the bus is active. After
the sequence has completed, the PEN, RSEN and
SEN bit will be clear, indicating the bus is Idle.
Clearing and setting the SSPEN bit will also reset
the I
SEN status bits.
Date Codes that pertain to this issue:
All engineering and production devices.
2
2
C Master mode, the BRG value of ‘0’ may not
C Master mode, the RCEN bit is set by soft-
2
C peripheral and clear the PEN, RSEN and
CY
© 2007 Microchip Technology Inc.
when using MPLAB
CY
®
to clear
ICD 2