PIC16C62A-20I/SO Microchip Technology, PIC16C62A-20I/SO Datasheet - Page 49
![IC MCU OTP 2KX14 PWM 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC16C62A-20I/SO
Manufacturer Part Number
PIC16C62A-20I/SO
Description
IC MCU OTP 2KX14 PWM 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16LF627A-IP.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16LC62A-04SP.pdf
(337 pages)
4.PIC16C62A-04SP.pdf
(8 pages)
Specifications of PIC16C62A-20I/SO
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
- PIC16LF627A-IP PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC16LC62A-04SP PDF datasheet #3
- PIC16C62A-04SP PDF datasheet #4
- Current page: 49 of 337
- Download datasheet (3Mb)
Example 4-1 shows the calling of a subroutine in
page 1 of the program memory. This example assumes
that the PCLATH is saved and restored by the interrupt
service routine (if interrupts are used).
EXAMPLE 4-1:
ORG 0x500
BSF
BCF
CALL
ORG 0x900
SUB1_P1:
RETURN
FIGURE 4-25: DIRECT/INDIRECT ADDRESSING
1997 Microchip Technology Inc.
bank select
RP1: RP0
For memory map detail see Figure 4-5, Figure 4-6, Figure 4-7, and Figure 4-8.
PCLATH,3
PCLATH,4
SUB1_P1
:
:
:
:
:
Direct Addressing
location select
6
Data
Memory
CALL OF A SUBROUTINE IN
PAGE 1 FROM PAGE 0
;Select page 1 (800h-FFFh)
;Only on >4K devices
;Call subroutine in
;page 1 (800h-FFFh)
;called subroutine
;page 1 (800h-FFFh)
;return to Call subroutine
;in page 0 (000h-7FFh)
from opcode
00h
7Fh
Bank 0
00
0
80h
FFh
Bank 1
01
100h
17Fh
Bank 2
10
4.5
The INDF register is not a physical register. Address-
ing the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF reg-
ister. Any instruction using the INDF register actually
accesses the register pointed to by the File Select Reg-
ister, FSR. Reading the INDF register itself indirectly
(FSR = '0') will produce 00h. Writing to the INDF regis-
ter indirectly results in a no-operation (although status
bits may be affected). An effective 9-bit address is
obtained by concatenating the 8-bit FSR register and
the IRP bit (STATUS<7>), as shown in Figure 4-25.
A simple program to clear RAM location 20h-2Fh using
indirect addressing is shown in Example 4-2.
EXAMPLE 4-2:
NEXT
CONTINUE
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
180h
1FFh
Bank 3
11
Indirect Addressing, INDF and FSR
Registers
clrf
movlw
movwf
incf
btfss
goto
:
IRP
bank select
7
INDIRECT ADDRESSING
0x20
FSR
INDF
FSR,F
FSR,4
NEXT
Indirect Addressing
PIC16C6X
;clear INDF register
;initialize pointer
;
;inc pointer
;all done?
;NO, clear next
;YES, continue
FSR
to RAM
DS30234D-page 49
location select
0
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