ATMEGA8-16PU Atmel, ATMEGA8-16PU Datasheet
ATMEGA8-16PU
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ATMEGA8-16PU Summary of contents
Page 1
... Operating Voltages – 2.7 - 5.5V (ATmega8L) – 4.5 - 5.5V (ATmega8) • Speed Grades – MHz (ATmega8L) – MHz (ATmega8) • Power Consumption at 4 Mhz, 3V, 25°C – Active: 3.6 mA – Idle Mode: 1.0 mA – Power-down Mode: 0.5 µA ® 8-bit Microcontroller ...
Page 2
... Pin Configurations ATmega8(L) 2 PDIP (RESET) PC6 1 28 PC5 (ADC5/SCL) (RXD) PD0 2 27 PC4 (ADC4/SDA) (TXD) PD1 3 26 PC3 (ADC3) (INT0) PD2 4 25 PC2 (ADC2) (INT1) PD3 5 24 PC1 (ADC1) (XCK/T0) PD4 6 23 PC0 (ADC0) VCC 7 22 GND GND 8 21 AREF (XTAL1/TOSC1) PB6 ...
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... Overview Block Diagram 2486O–AVR–10/04 The ATmega8 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega8 achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed. ...
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... Programmable Flash on a monolithic chip, the Atmel ATmega8 is a powerful microcon- troller that provides a highly-flexible and cost-effective solution to many embedded control applications. The ATmega8 AVR is supported with a full suite of program and system development tools, including C compilers, macro assemblers, program debugger/simulators, In-Cir- cuit Emulators, and evaluation kits. ...
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... The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega8 as listed on page 61. Reset input. A low level on this pin for longer than the minimum pulse length will gener- ate a reset, even if the clock is not running ...
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... AV CC AREF ADC7..6 (TQFP and MLF Package Only) About Code Examples ATmega8( the supply voltage pin for the A/D Converter, Port C (3..0), and ADC (7..6 should be externally connected should be connected to V through a low-pass filter. Note that Port C (5..4) use digital CC supply voltage, V ...
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... This allows single-cycle Arithmetic Logic Unit (ALU) operation typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. ATmega8(L) Data Bus 8-bit Status and Control ...
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... ATmega8(L) 8 Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash Pro- gram memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section ...
Page 9
... The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information. • Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 1 – Z: Zero Flag ATmega8( ...
Page 10
... General Purpose Register File ATmega8(L) 10 The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a Carry in an arithmetic or logic operation. See the “Instruc- tion Set Description” ...
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... AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. Bit SP15 SP14 SP13 SP7 SP6 SP5 Read/Write R/W R/W R/W R/W R/W R/W Initial Value ATmega8( R26 (0x1A R28 (0x1C R30 (0x1E SP12 SP11 SP10 SP9 SP4 SP3 SP2 SP1 4 ...
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... Instruction Execution Timing Reset and Interrupt Handling ATmega8(L) 12 This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk source for the chip. No internal clock division is used. Figure 5 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept ...
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... EECR, EEWE out SREG, r16 ; restore SREG value (I-bit) C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1<<EEMWE); /* start EEPROM write */ EECR |= (1<<EEWE); SREG = cSREG; /* restore SREG value (I-bit) */ ATmega8(L) 13 ...
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... Interrupt Response Time ATmega8(L) 14 When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in the following example. Assembly Code Example sei ; set global interrupt enable sleep; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ...
Page 15
... Boot Program section and Application Program section. The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega8 Program Counter (PC bits wide, thus addressing the 4K Program mem- ory locations. The operation of Boot Program section and associated Boot Lock Bits for software protection are described in detail in “ ...
Page 16
... X, Y and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and the 1024 bytes of inter- nal data SRAM in the ATmega8 are all accessible through all these addressing modes. The Register File is described in “General Purpose Register File” on page 10. ...
Page 17
... Data RD Memory Vccess Instruction The ATmega8 contains 512 bytes of data EEPROM memory organized as a sepa- rate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described bellow, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register. “ ...
Page 18
... Bits 7..4 – Res: Reserved Bits These bits are reserved bits in the ATmega8 and will always read as zero. • Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared. • ...
Page 19
... The calibrated Oscillator is used to time the EEPROM accesses. Table 1 lists the typical programming time for EEPROM access from the CPU. Table 1. EEPROM Programming Time Number of Calibrated RC Symbol EEPROM Write (from CPU) Note: 1. Uses 1 MHz clock, independent of CKSEL Fuse settings. ATmega8(L) (1) Oscillator Cycles Typ Programming Time 8448 8 ...
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... ATmega8(L) 20 The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (for example by dis- abling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash boot loader is present in the soft- ware ...
Page 21
... EEPROM, and the same design solutions should be applied. An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Second, the CPU itself can execute instructions incorrectly, if the sup- ply voltage is too low recommendation: ATmega8(L) 21 ...
Page 22
... The I/O space definition of the ATmega8 is shown in “” on page 284. All ATmega8 I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions, transferring data between the 32 general pur- pose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions ...
Page 23
... I/O clock is halted. Also note that address recognition in the TWI module is carried out asynchronously when clk tion in all sleep modes. The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock. ATmega8(L) ADC CPU Core RAM clk ...
Page 24
... The number of WDT Oscillator cycles used for each time-out is shown in Table 3. The frequency of the Watchdog Oscil- lator is voltage dependent as shown in “ATmega8 Typical Characteristics”. The device is shipped with CKSEL = “0001” and SUT = “10” (1 MHz Internal RC Oscillator, slowly ris- ing power) ...
Page 25
... Note: 1. This option should not be used with crystals, only with ceramic resonators. The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table 5. ATmega8(L) C2 XTAL2 C1 XTAL1 GND Recommended Range for Capacitors C1 and C2 for Use with Crystals (pF) – ...
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... Low-frequency Crystal Oscillator ATmega8(L) 26 Table 5. Start-up Times for the Crystal Oscillator Clock Selection Start-up Time from Power-down CKSEL0 SUT1..0 and Power-save ( 258 CK ( 258 16K 16K 16K CK Notes: 1. These options should only be used when not operating close to the maximum fre- quency of the device, and only if frequency stability at start-up is not important for the application ...
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... Start-up Time from Power-down and SUT1..0 Power-save ( Note: 1. This option should not be used when operating close to the maximum frequency of the device. ATmega8(L) NC XTAL2 XTAL1 GND Frequency Range (MHz) 0.1 - 0.9 0.9 - 3.0 3.0 - 8.0 8.0 - 12.0 Additional Delay from Reset (V = 5.0V) Recommended Usage CC – ...
Page 28
... Calibrated Internal RC Oscillator ATmega8(L) 28 The calibrated internal RC Oscillator provides a fixed 1.0, 2.0, 4.0, or 8.0 MHz clock. All frequencies are nominal values at 5V and 25°C. This clock may be selected as the sys- tem clock by programming the CKSEL Fuses as shown in Table 9. If selected, it will operate with no external components ...
Page 29
... Otherwise, the EEPROM or Flash write may fail. Note that the Oscillator is intended for calibration to 1.0, 2.0, 4.0, or 8.0 MHz. Tuning to other values is not guaranteed, as indicated in Table 11. Table 11. Internal RC Oscillator Frequency Range Min Frequency in Percentage of OSCCAL Value Nominal Frequency (%) 0x00 0x7F 0xFF ATmega8( CAL4 CAL3 CAL2 CAL1 R/W ...
Page 30
... External Clock Timer/Counter Oscillator ATmega8( drive the device from an external clock source, XTAL1 should be driven as shown in Figure 13. To run the device on an external clock, the CKSEL Fuses must be pro- grammed to “0000”. By programming the CKOPT Fuse, the user can enable an internal 36 pF capacitor between XTAL1 and GND ...
Page 31
... Reset Vector. Note that the Extended Standby mode present in many other AVR MCUs has been removed in the ATmega8, as the TOSC and XTAL inputs share the same physical pins. Figure 10 on page 23 presents the different clock systems in the ATmega8, and their distribution ...
Page 32
... ADC Noise Reduction Mode Power-down Mode Power-save Mode ATmega8(L) 32 When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing SPI, USART, Analog Comparator, ADC, Two- wire Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating ...
Page 33
... Analog Comparator is set up to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Ref- erence will be enabled, independent of sleep mode. Refer to “Analog Comparator” on page 190 for details on how to configure the Analog Comparator. ATmega8(L) , allowing operation only of asyn- ASY Wake-up Sources ...
Page 34
... Brown-out Detector Internal Voltage Reference Watchdog Timer Port Pins ATmega8( the Brown-out Detector is not needed in the application, this module should be turned off. If the Brown-out Detector is enabled by the BODEN Fuse, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to “ ...
Page 35
... The time-out period of the delay counter is defined by the user through the CKSEL Fuses. The different selections for the delay period are presented in “Clock Sources” on page 24. The ATmega8 has four sources of Reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V ) ...
Page 36
... V production test. This guarantees that a Brown-out Reset will occur before voltage where correct operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL = 1 for ATmega8L and BODLEVEL = 0 for ATmega8. BODLEVEL = 1 is not applicable for ATmega8. DATA BUS ...
Page 37
... V CC Figure 15. MCU Start-up, RESET Tied POT RST RESET t TOUT TIME-OUT INTERNAL RESET Figure 16. MCU Start-up, RESET Extended Externally V POT V CC RESET TIME-OUT INTERNAL RESET ATmega8(L) rise. The RESET signal is activated CC decreases below the detection level RST t TOUT is below the CC 37 ...
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... MCU after the time-out period t Figure 17. External Reset During Operation CC ATmega8 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the fuse BODLEVEL to be 2.7V (BODLEVEL unprogrammed ...
Page 39
... Bit 7..4 – Res: Reserved Bits These bits are reserved bits in the ATmega8 and always read as zero. • Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. ...
Page 40
... Signals and Start-up Time ATmega8(L) 40 ATmega8 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. The 2.56V reference to the ADC is generated from the internal bandgap reference. The voltage reference has a start-up time that may influence the way it should be used. ...
Page 41
... Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the ATmega8 and will always read as zero. • Bit 4 – WDCE: Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled ...
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... ATmega8(L) 42 • Bit 3 – WDE: Watchdog Enable When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit has logic level one. To disable an enabled Watchdog Timer, the follow- ing procedure must be followed: 1 ...
Page 43
... In the same operation, write a logical one to WDCE and WDE. Even though the WDE always is set, the WDE must be written to one to start the timed sequence. Within the next four clock cycles, in the same operation, write the WDP bits as desired, but with the WDCE bit cleared. The value written to the WDE bit is irrelevant. ATmega8(L) 43 ...
Page 44
... Interrupts Interrupt Vectors in ATmega8 ATmega8(L) 44 This section describes the specifics of the interrupt handling performed by the ATmega8. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 12. Table 18. Reset and Interrupt Vectors Program (2) Vector No. Address Source (1) 1 0x000 ...
Page 45
... The Boot Reset Address is shown in Table 82 on page 217. For the BOOTRST Fuse “1” means unprogrammed while “0” means programmed. The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega8 is: addressLabels Code $000 rjmp ...
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... ATmega8(L) 46 When the BOOTRST Fuse is unprogrammed, the boot section size set to 2K bytes and the IVSEL bit in the GICR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: ...
Page 47
... Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is pro- gramed, interrupts are disabled while executing from the Boot Loader section. Refer to the section “Boot Loader Support – Read-While-Write Self-Programming” on page 206 for details on Boot Lock Bits. ATmega8(L) Comments ; Reset handler ; IRQ0 Handler ...
Page 48
... ATmega8(L) 48 • Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below ...
Page 49
... Port Functions” on page 54. Refer to the individual module sections for a full description of the alternate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. ATmega8( Logic See Figure " ...
Page 50
... Ports as General Digital I/O Configuring the Pin ATmega8(L) 50 The ports are bi-directional I/O ports with optional internal pull-ups. Figure 22 shows a functional description of one I/O port pin, here generically called Pxn. (1) Figure 22. General Digital I/O Pxn PUD: PULLUP DISABLE SLEEP: SLEEP CONTROL ...
Page 51
... The maximum and minimum propagation delays are denoted respectively. pd,min Figure 23. Synchronization when Reading an Externally Applied Pin Value SYSTEM CLK INSTRUCTIONS XXX SYNC LATCH PINxn r17 ATmega8(L) I/O Pull-up Comment Input No Tri-state (Hi-Z) Pxn will source current if external Input Yes pulled low. ...
Page 52
... ATmega8(L) 52 Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low ...
Page 53
... Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned sleep modes, as the clamping in these sleep modes produces the requested logic change. ATmega8(L) 53 ...
Page 54
... Unconnected pins Alternate Port Functions ATmega8( some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). ...
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... The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details. ATmega8(L) Description If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010 ...
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... Special Function IO Register – SFIOR Alternate Functions of Port B ATmega8(L) 56 Bit Read/Write Initial Value • Bit 2 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). ...
Page 57
... ICP1 – Input Capture Pin: The PB0 pin can act as an Input Capture Pin for Timer/Counter1. Table 23 and Table 24 relate the alternate functions of Port B to the overriding signals shown in Figure 25 on page 54. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. ATmega8(L) 57 ...
Page 58
... ATmega8(L) 58 Table 23. Overriding Signals for Alternate Functions in PB7..PB4 Signal PB7/XTAL2/ PB6/XTAL1/ (1)(2) Name TOSC2 TOSC1 PUOE EXT • (INTRC + INTRC + AS2 AS2) PUO 0 0 DDOE EXT • (INTRC + INTRC + AS2 AS2) DDOV 0 0 PVOE 0 0 PVOV 0 0 DIEOE EXT • (INTRC + ...
Page 59
... PC3 can also be used as ADC input Channel 3. Note that ADC input channel 3 uses analog power. • ADC2 – Port C, Bit 2 PC2 can also be used as ADC input Channel 2. Note that ADC input channel 2 uses analog power. • ADC1 – Port C, Bit 1 ATmega8(L) 59 ...
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... ATmega8(L) 60 PC1 can also be used as ADC input Channel 1. Note that ADC input channel 1 uses analog power. • ADC0 – Port C, Bit 0 PC0 can also be used as ADC input Channel 0. Note that ADC input channel 0 uses analog power. Table 26 and Table 27 relate the alternate functions of Port C to the overriding signals shown in Figure 25 on page 54 ...
Page 61
... RXD – Port D, Bit 0 RXD, Receive Data (Data input pin for the USART). When the USART Receiver is enabled this pin is configured as an input regardless of the value of DDD0. When the USART forces this pin input, the pull-up can still be controlled by the PORTD0 bit. ATmega8(L) 61 ...
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... ATmega8(L) 62 Table 29 and Table 30 relate the alternate functions of Port D to the overriding signals shown in Figure 25 on page 54. Table 29. Overriding Signals for Alternate Functions PD7..PD4 Signal Name PD7/AIN1 PD6/AIN0 PUOE 0 0 PUO 0 0 OOE PVOE 0 0 PVO 0 0 DIEOE 0 0 DIEO ...
Page 63
... R/W R/W R/W Initial Value Bit DDD7 DDD6 DDD5 Read/Write R/W R/W R/W Initial Value Bit PIND7 PIND6 PIND5 Read/Write Initial Value N/A N/A N/A ATmega8( PORTB4 PORTB3 PORTB2 PORTB1 R/W R/W R/W R DDB4 DDB3 DDB2 DDB1 R/W R/W R/W R PINB4 ...
Page 64
... External Interrupts MCU Control Register – MCUCR ATmega8(L) 64 The external interrupts are triggered by the INT0, and INT1 pins. Observe that, if enabled, the interrupts will trigger even if the INT0..1 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the MCU Control Register – ...
Page 65
... ISC00) in the MCU general Control Register (MCUCR) define whether the external interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from the INT0 Inter- rupt Vector. ATmega8( – ...
Page 66
... General Interrupt Flag Register – GIFR ATmega8(L) 66 Bit INTF1 INTF0 – Read/Write R/W R/W R Initial Value • Bit 7 – INTF1: External Interrupt Flag 1 When an event on the INT1 pin triggers an interrupt request, INTF1 becomes set (one). If the I-bit in SREG and the INT1 bit in GICR are set (one), the MCU will jump to the cor- responding Interrupt Vector ...
Page 67
... Timer/Counter0 counter value and so on. The definitions in Table 33 are also used extensively throughout this datasheet. Table 33. Definitions BOTTOM The counter reaches the BOTTOM when it becomes 0x00 MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255) ATmega8(L) TCCRn Clock Select clk Tn Edge Detector ...
Page 68
... Timer/Counter Clock Sources Counter Unit Operation ATmega8(L) 68 The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the clock select logic which is controlled by the clock select (CS02:0) bits located in the Timer/Counter Control Register (TCCR0). For details on clock sources and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on page 72 ...
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... Tn (clk /1) I/O TCNTn MAX - 1 TOVn Figure 29 shows the same timing data, but with the prescaler enabled. Figure 29. Timer/Counter Timing Diagram, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn MAX - 1 TOVn ATmega8(L) T0 MAX BOTTOM /8) clk_I/O MAX BOTTOM ) is therefore BOTTOM + 1 BOTTOM + 1 69 ...
Page 70
... Timer/Counter Register Description Timer/Counter Control Register – TCCR0 Timer/Counter Register – TCNT0 Timer/Counter Interrupt Mask Register – TIMSK ATmega8(L) 70 Bit – – – Read/Write Initial Value • Bit 2:0 – CS02:0: Clock Select The three clock select bits select the clock source to be used by the Timer/Counter. ...
Page 71
... The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt Handling Vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. ATmega8( ...
Page 72
... Timer/Counter1 Prescalers Internal Clock Source Prescaler Reset External Clock Source ATmega8(L) 72 Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. The Timer/Counter can be clocked directly by the system clock (by setting the CSn2 ...
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... The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. This bit will always be read as zero. ATmega8(L) < f /2) given a 50/50% duty cycle. Since ExtClk clk_I/O /2 ...
Page 74
... Timer/Counter1 Overview ATmega8(L) 74 The 16-bit Timer/Counter unit allows accurate program execution timing (event man- agement), wave generation, and signal timing measurement. The main features are: • True 16-bit Design (i.e., allows 16-bit PWM) • Two Independent Output Compare Units • ...
Page 75
... The double buffered Output Compare Registers (OCR1A/B) are compared with the Timer/Counter value at all time. The result of the compare can be used by the waveform generator to generate a PWM or variable frequency output on the Output Compare Pin (OC1A/B). See “Output Compare Units” on page 83. The Compare Match event will also ATmega8(L) (1) TOVn (Int. Req.) ...
Page 76
... Definitions Compatibility ATmega8(L) 76 set the Compare Match Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture Pin (ICP1 the Analog Compar- ator pins (see “ ...
Page 77
... Timer Registers, then the result of the access outside the interrupt will be corrupted. Therefore, when both the main code and the interrupt code update the temporary regis- ter, the main code must disable the interrupts during the 16-bit access. ATmega8(L) 77 ...
Page 78
... ATmega8(L) 78 The following code examples show how atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle. (1) Assembly Code Example TIM16_ReadTCNT1: ; Save Global Interrupt Flag in r18,SREG ; Disable interrupts cli ; Read TCNT1 into r17:r16 ...
Page 79
... If writing to more than one 16-bit register where the High byte is the same for all regis- ters written, then the High byte only needs to be written once. However, note that the same rule of atomic operation described previously also applies in this case. ATmega8(L) 79 ...
Page 80
... Timer/Counter Clock Sources Counter Unit ATmega8(L) 80 The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the clock select logic which is controlled by the clock select (CS12:0) bits located in the Timer/Counter Control Register B (TCCR1B). For details on clock sources and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on page 72 ...
Page 81
... ICR1 Register. If enabled (TICIE1 = 1), the Input Capture Flag generates an Input Capture interrupt. The ICF1 Flag is automatically cleared when the interrupt is executed. Alternatively the ICF1 Flag can be cleared by software by writing a logical one to its I/O bit location. ATmega8(L) DATA BUS (8-bit) TCNTnH (8-bit) ...
Page 82
... Input Capture Pin Source Noise Canceler Using the Input Capture Unit ATmega8(L) 82 Reading the 16-bit value in the Input Capture Register (ICR1) is done by first reading the Low byte (ICR1L) and then the High byte (ICR1H). When the Low byte is read the High byte is copied into the High byte temporary register (TEMP) ...
Page 83
... The OCR1x Register is double buffered when using any of the twelve Pulse Width Mod- ulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the ATmega8(L) DATA BUS (8-bit) TCNTnH (8-bit) ...
Page 84
... Force Output Compare Compare Match Blocking by TCNT1 Write Using the Output Compare Unit ATmega8(L) 84 update of the OCR1x Compare Register to either TOP or BOTTOM of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR1x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR1x Buffer Register, and if double buffering is disabled the CPU will access the OCR1x directly ...
Page 85
... The design of the Output Compare Pin logic allows initialization of the OC1x state before the output is enabled. Note that some COM1x1:0 bit settings are reserved for certain modes of operation. See “16-bit Timer/Counter Register Description” on page 95. The COM1x1:0 bits have no effect on the Input Capture unit. ATmega8( OCnx ...
Page 86
... Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode ATmega8(L) 86 The waveform generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM1x1 tells the waveform generator that no action on the OC1x Register performed on the next Compare Match. For com- pare output actions in the non-PWM modes refer to Table 36 on page 95 ...
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... PWM mode can be twice as high as the phase correct and phase and frequency correct PWM modes that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High fre- ATmega8(L) OCnA Interrupt Flag Set or ICFn Interrupt Flag Set ...
Page 88
... ATmega8(L) 88 quency allows physically small sized external components (coils, capacitors), hence reduces total system cost. The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM ...
Page 89
... PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or ATmega8(L) f clk_I/O = ---------------------------------- - ⋅ ...
Page 90
... ATmega8(L) 90 OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation: R PCPWM In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13 3), the value in ICR1 (WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11) ...
Page 91
... OCR1A set to MAX). The PWM resolution in bits can be calculated using the following equation: R PFCPWM In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A ATmega8(L) f clk_I/O = --------------------------- - ⋅ ...
Page 92
... ATmega8(L) 92 (WGM13:0 = 9). The counter has then reached the TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency correct PWM mode is shown on Figure 40. The figure shows phase and frequency correct PWM mode when OCR1A or ICR1 is used to define TOP ...
Page 93
... OCF1x. Figure 41. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling clk I/O clk Tn (clk /1) I/O TCNTn OCRnx - 1 OCRnx OCFnx Figure 42 shows the same timing data, but with the prescaler enabled. ATmega8(L) f clk_I/O = --------------------------- - ⋅ ⋅ TOP T1 OCRnx OCRnx + 1 OCRnx Value ) is therefore OCRnx + 2 ...
Page 94
... ATmega8(L) 94 Figure 42. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn OCRnx - 1 OCRnx OCFnx Figure 43 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on ...
Page 95
... COM1B0 Description 0 0 Normal port operation, OC1A/OC1B disconnected Toggle OC1A/OC1B on Compare Match 1 0 Clear OC1A/OC1B on Compare Match (Set output to low level Set OC1A/OC1B on Compare Match (Set output to high level) ATmega8(L) /8) clk_I/O TOP BOTTOM TOP TOP - 1 New OCRnx Value COM1B0 FOC1A FOC1B ...
Page 96
... ATmega8(L) 96 Table 37 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast PWM mode. Table 37. Compare Output Mode, Fast PWM COM1A1/ COM1A0/ COM1B1 COM1B0 Description 0 0 Normal port operation, OC1A/OC1B disconnected WGM13:0 = 15: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected ...
Page 97
... PWM, Phase and Frequency Correct 1 0 PWM, Phase Correct 1 1 PWM, Phase Correct 0 0 CTC 0 1 (Reserved Fast PWM 1 1 Fast PWM ATmega8(L) Update of x TOP OCR1 0xFFFF Immediate 0x00FF TOP 0x01FF TOP 0x03FF TOP OCR1A Immediate 0x00FF TOP 0x01FF TOP ...
Page 98
... Timer/Counter 1 Control Register B – TCCR1B ATmega8(L) 98 Bit ICNC1 ICES1 – Read/Write R/W R/W R Initial Value • Bit 7 – ICNC1: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise can- celer is activated, the input from the Input Capture Pin (ICP1) is filtered. The filter function requires four successive equal valued samples of the ICP1 pin for changing its output ...
Page 99
... The Output Compare Registers are 16-bit in size. To ensure that both the high and Low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 77. ATmega8( ...
Page 100
... Input Capture Register 1 – ICR1H and ICR1L Timer/Counter Interrupt Mask (1) Register – TIMSK ATmega8(L) 100 Bit Read/Write R/W R/W R/W Initial Value The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator Output for Timer/Counter1). ...
Page 101
... TOV1 Flag is set when the timer overflows. Refer to Table 39 on page 97 for the TOV1 Flag behavior when using another WGM13:0 bit setting. TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. ATmega8( ...
Page 102
... Timer/Counter2 with PWM and Asynchronous Operation Overview ATmega8(L) 102 Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, phase Correct Pulse Width Modulator (PWM) • ...
Page 103
... When the AS2 bit in the ASSR Register is written to logic one, the clock source is taken from the Timer/Counter Oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation, see “Asynchronous Status Register – ASSR” on page 117. For details on clock sources and prescaler, see “Timer/Counter Prescaler” on page 121. ATmega8( default equal to the MCU clock, clk T2 ...
Page 104
... Counter Unit ATmega8(L) 104 The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 46 shows a block diagram of the counter and its surrounding environment. Figure 46. Counter Unit Block Diagram DATA BUS count clear TCNTn Control Logic direction BOTTOM Signal description (internal signals): count Increment or decrement TCNT2 by 1 ...
Page 105
... The OCR2 Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR2 Buffer Register, and if double buffering is disabled the CPU will access the OCR2 directly. ATmega8(L) DATA BUS TCNTn = (8-bit Comparator ) OCFn (Int ...
Page 106
... Compare Match Blocking by TCNT2 Write Using the Output Compare Unit ATmega8(L) 106 In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC2) bit. Forcing Compare Match will not set the OCF2 Flag or reload/clear the timer, but the OC2 pin will be updated real Compare Match had occurred (the COM21:0 bits settings define whether the OC2 pin is set, cleared or toggled) ...
Page 107
... Waveform Generation mode. The design of the Output Compare Pin logic allows initialization of the OC2 state before the output is enabled. Note that some COM21:0 bit settings are reserved for certain modes of operation. See “8-bit Timer/Counter Register Description” on page 115. ATmega8( ...
Page 108
... Compare Output Mode and Waveform Generation Modes of Operation Normal Mode ATmega8(L) 108 The Waveform Generator uses the COM21:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM21 tells the waveform generator that no action on the OC2 Register performed on the next Compare Match. For com- pare output actions in the non-PWM modes refer to Table 43 on page 116 ...
Page 109
... OCn The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). As for the Normal mode of operation, the TOV2 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x00. ATmega8(L) OCn Interrupt Flag Set ...
Page 110
... Fast PWM Mode ATmega8(L) 110 The fast Pulse Width Modulation or fast PWM mode (WGM21 provides a high fre- quency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to MAX then restarts from BOTTOM ...
Page 111
... PWM mode is shown on Figure 51. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes repre- sent compare matches between OCR2 and TCNT2. ATmega8(L) f clk_I/O f ...
Page 112
... ATmega8(L) 112 Figure 51. Phase Correct PWM Mode, Timing Diagram TCNTn OCn OCn Period 1 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOT- TOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. ...
Page 113
... Figure 53 shows the same timing data, but with the prescaler enabled. Figure 53. Timer/Counter Timing Diagram, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn MAX - 1 TOVn Figure 54 shows the setting of OCF2 in all modes except CTC mode. ATmega8(L) MAX BOTTOM /8) clk_I/O MAX BOTTOM should I/O BOTTOM + 1 BOTTOM + 1 113 ...
Page 114
... ATmega8(L) 114 Figure 54. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn OCRn - 1 OCRn OCFn Figure 55 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode. Figure 55. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Prescaler (f ...
Page 115
... OC2 pin must be set in order to enable the output driver. When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0 bit setting. Table 43 shows the COM21:0 bit functionality when the WGM21:0 bits are set to a normal or CTC mode (non-PWM). ATmega8( ...
Page 116
... ATmega8(L) 116 Table 43. Compare Output Mode, Non-PWM Mode COM21 COM20 Description 0 0 Normal port operation, OC2 disconnected Toggle OC2 on Compare Match 1 0 Clear OC2 on Compare Match 1 1 Set OC2 on Compare Match Table 44 shows the COM21:0 bit functionality when the WGM21:0 bits are set to fast PWM mode ...
Page 117
... When AS2 is written to zero, Timer/Counter 2 is clocked from the I/O clock, clk AS2 is written to one, Timer/Counter 2 is clocked from a crystal Oscillator connected to the Timer Oscillator 1 (TOSC1) pin. When the value of AS2 is changed, the contents of TCNT2, OCR2, and TCCR2 might be corrupted. ATmega8(L) Description No clock source (Timer/Counter stopped). clk ...
Page 118
... Asynchronous Operation of Timer/Counter2 ATmega8(L) 118 • Bit 2 – TCN2UB: Timer/Counter2 Update Busy When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set. When TCNT2 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCNT2 is ready to be updated with a new value. • ...
Page 119
... Interrupt Flag. The Output Compare Pin is changed on the timer clock and is not synchronized to the processor clock. ATmega8(L) ) again becomes active, TCNT2 will I/O 119 ...
Page 120
... Timer/Counter Interrupt Mask Register – TIMSK Timer/Counter Interrupt Flag Register – TIFR ATmega8(L) 120 Bit OCIE2 TOIE2 TICIE1 Read/Write R/W R/W R/W Initial Value • Bit 7 – OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable When the OCIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match interrupt is enabled ...
Page 121
... Writing a zero to this bit will have no effect. This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock. If this bit is written when Timer/Counter2 is operating in Asynchronous mode, the bit will remain one until the prescaler has been reset. ATmega8(L) 10-BIT T/C PRESCALER Clear 0 ...
Page 122
... Serial Peripheral Interface – SPI ATmega8(L) 122 The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega8 and peripheral devices or between several AVR devices. The ATmega8 SPI includes the following features: • Full-duplex, Three-wire Synchronous Data Transfer • ...
Page 123
... User Defined MISO Input SCK User Defined SS User Defined Note: 1. See “Port B Pins Alternate Functions” on page 56 for a detailed description of how to define the direction of the user defined SPI pins. ATmega8(L) MSB SLAVE MISO MISO 8 BIT SHIFT REGISTER MOSI MOSI SCK SCK ...
Page 124
... ATmega8(L) 124 The following code examples show how to initialize the SPI as a Master and how to per- form a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB ...
Page 125
... Set MISO output, all others input */ DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); } char SPI_SlaveReceive(void Wait for reception complete */ while(!(SPSR & (1<<SPIF))) ; /* Return data register */ return SPDR; } Note: 1. The example code assumes that the part specific header file is included. ATmega8(L) 125 ...
Page 126
... SS Pin Functionality Slave Mode Master Mode SPI Control Register – SPCR ATmega8(L) 126 When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data ...
Page 127
... SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency f is shown in the following table: osc Table 50. Relationship Between SCK and the Oscillator Frequency SPI2X SPR1 ATmega8(L) Trailing Edge Trailing Edge Setup SPR0 SCK Frequency osc osc osc f / ...
Page 128
... SPI is in Master mode (see Table 50). This means that the minimum SCK period will be 2 CPU clock periods. When the SPI is configured as Slave, the SPI is only guaran- teed to work lower. osc The SPI interface on the ATmega8 is also used for Program memory and EEPROM downloading or uploading. See page 234 for Serial Programming and verification. Bit 7 6 ...
Page 129
... SCK (CPOL = 0) mode 1 SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB LSB first (DORD = 1) LSB ATmega8(L) Trailing Edge Setup (Falling) Sample (Falling) Setup (Rising) Sample (Rising) Bit 5 Bit 4 Bit 3 Bit 2 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 ...
Page 130
... USART Overview ATmega8(L) 130 The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART highly-flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • ...
Page 131
... U2X found in the UCSRA Register. When using Synchronous mode (UMSEL = 1), the Data Direction Register for the XCK pin (DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCK pin is only active when using Synchronous mode. Figure 62 shows a block diagram of the clock generation logic. ATmega8(L) 131 ...
Page 132
... Internal Clock Generation – The Baud Rate Generator ATmega8(L) 132 Figure 62. Clock Generation Logic, Block Diagram UBRR UBRR+1 Prescaling Down-Counter OSC Sync Register xcki XCK xcko Pin DDR_XCK Signal description: txclk Transmitter clock. (Internal Signal) rxclk Receiver base clock. (Internal Signal) xcki Input from XCK pin (internal Signal) ...
Page 133
... Receiver. This process introduces a two CPU clock period delay and therefore the max- imum external XCK clock frequency is limited by the following equation: Note that f depends on the stability of the system clock source therefore recom- osc mended to add some margin to avoid possible loss of data due to frequency variations. ATmega8(L) Equation for Calculating (1) Baud Rate UBRR Value f ...
Page 134
... Synchronous Clock Operation When Synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock Frame Formats ATmega8(L) 134 input (Slave) or clock output (Master). The dependency between the clock edges and data sampling or data change is the same. The basic principle is that data input (on RxD) is sampled at the opposite XCK clock edge of the edge the data output (TxD) is changed ...
Page 135
... For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 Registers. When the function writes to the UCSRC Register, the URSEL bit (MSB) must be set due to the sharing of I/O location by UBRRH and UCSRC. ATmega8(L) ⊕ … ⊕ ...
Page 136
... ATmega8(L) 136 (1) Assembly Code Example USART_Init: ; Set baud rate out UBRRH, r17 out UBRRL, r16 ; Enable Receiver and Transmitter ldi r16, (1<<RXEN)|(1<<TXEN) out UCSRB,r16 ; Set frame format: 8data, 2stop bit ldi r16, (1<<URSEL)|(1<<USBS)|(3<<UCSZ0) ...
Page 137
... The example codes assumes that the part specific header file is included. The function simply waits for the transmit buffer to be empty by checking the UDRE Flag, before loading it with new data to be transmitted. If the Data Register Empty Inter- rupt is utilized, the interrupt routine writes the data into the buffer. ATmega8(L) 137 ...
Page 138
... Sending Frames with 9 Data Bits Transmitter Flags and Interrupts ATmega8(L) 138 If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in UCSRB before the Low byte of the character is written to UDR. The following code examples show a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is assumed to be stored in registers R17:R16 ...
Page 139
... The disabling of the Transmitter (setting the TXEN to zero) will not become effective until ongoing and pending transmissions are completed (i.e., when the Transmit Shift Register and Transmit Buffer Register do not contain data to be transmitted). When dis- abled, the Transmitter will no longer override the TxD pin. ATmega8(L) 139 ...
Page 140
... Data Reception – The USART Receiver Receiving Frames with Data Bits ATmega8(L) 140 The USART Receiver is enabled by writing the Receive Enable (RXEN) bit in the UCSRB Register to one. When the Receiver is enabled, the normal pin operation of the RxD pin is overridden by the USART and given the function as the Receiver’s serial input ...
Page 141
... PE Status Flags as well. Read status from UCSRA, then data from UDR. Reading the UDR I/O location will change the state of the receive buffer FIFO and consequently the TXB8, FE, DOR, and PE bits, which all are stored in the FIFO, will change. ATmega8(L) 141 ...
Page 142
... ATmega8(L) 142 The following code example shows a simple USART receive function that handles both 9-bit characters and the status bits. (1) Assembly Code Example USART_Receive: ; Wait for data to be received sbis UCSRA, RXC rjmp USART_Receive ; Get status and ninth bit, then data from buffer ...
Page 143
... If parity check is not enabled the PE bit will always be read zero. For compatibility with future devices, always set this bit to zero when writing to UCSRA. For more details see “Parity Bit Calculation” on page 135 and “Parity Checker” on page 144. ATmega8(L) 143 ...
Page 144
... Asynchronous Data Reception Asynchronous Clock Recovery ATmega8(L) 144 The Parity Checker is active when the high USART Parity mode (UPM1) bit is set. Type of parity check to be performed (odd or even) is selected by the UPM0 bit. When enabled, the Parity Checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame ...
Page 145
... RxD pin. The recovery process is then repeated until a complete frame is received. Including the first stop bit. Note that the Receiver only uses the first stop bit of a frame. Figure 67 shows the sampling of the stop bit and the earliest possible beginning of the start bit of the next frame. ATmega8(L) START ...
Page 146
... Asynchronous Operational Range ATmega8(L) 146 Figure 67. Stop Bit Sampling and Next Start Bit Sampling RxD Sample (U2X = Sample (U2X = The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 value, the Frame Error (FE) Flag will be set. ...
Page 147
... The second source for the error is more controllable. The baud rate generator can not always do an exact division of the system frequency to get the baud rate wanted. In this case an UBRR value that gives an acceptable low error can be used if possible. ATmega8(L) Max Total Recommended Max (%) ...
Page 148
... Multi-processor Communication Mode Using MPCM ATmega8(L) 148 Setting the Multi-processor Communication mode (MPCM) bit in UCSRA enables a fil- tering function of incoming frames received by the USART Receiver. Frames that do not contain address information will be ignored and not put into the receive buffer. This effectively reduces the number of incoming frames that has to be handled by the CPU system with multiple MCUs that communicate via the same serial bus ...
Page 149
... UCSRC = (1<<URSEL)|(1<<USBS)|(1<<UCSZ1); ... Note: 1. The example code assumes that the part specific header file is included. As the code examples illustrate, write accesses of the two registers are relatively unaf- fected of the sharing of I/O location. ATmega8(L) 149 ...
Page 150
... USART Register Description USART I/O Data Register – UDR ATmega8(L) 150 Doing a read access to the UBRRH or the UCSRC Register is a more complex opera- tion. However, in most applications rarely necessary to read any of these registers. The read access is controlled by a timed sequence. Reading the I/O location once returns the UBRRH Register contents ...
Page 151
... This bit is set if the next character in the receive buffer had a Parity Error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR) is read. Always set this bit to zero when writing to UCSRA. • Bit 1 – U2X: Double the USART transmission speed ATmega8( ...
Page 152
... USART Control and Status Register B – UCSRB ATmega8(L) 152 This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from effec- tively doubling the transfer rate for asynchronous communication. ...
Page 153
... UCSRC. The URSEL must be one when writing the UCSRC. • Bit 6 – UMSEL: USART Mode Select This bit selects between Asynchronous and Synchronous mode of operation. Table 55. UMSEL Bit Settings UMSEL Mode 0 Asynchronous Operation 1 Synchronous Operation ATmega8( UPM0 USBS UCSZ1 UCSZ0 UCPOL ...
Page 154
... ATmega8(L) 154 • Bit 5:4 – UPM1:0: Parity Mode These bits enable and set type of Parity Generation and Check. If enabled, the Trans- mitter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver will generate a parity value for the incoming data and com- pare it to the UPM0 setting ...
Page 155
... UBRRL contains the eight least significant bits of the USART baud rate. Ongoing transmissions by the Transmitter and Receiver will be cor- rupted if the baud rate is changed. Writing UBRRL will trigger an immediate update of the baud rate prescaler. ATmega8(L) Received Data Sampled (Input on RxD Pin) Falling XCK Edge ...
Page 156
... UBRR = 0, Error = 0.0% ATmega8(L) 156 For standard crystal and resonator frequencies, the most commonly used baud rates for asynchronous operation can be generated by using the UBRR settings in Table 60. UBRR values which yield an actual baud rate differing less than 0.5% from the target baud rate, are bold in the table ...
Page 157
... ATmega8( 7.3728 MHz osc U2X = 1 U2X = 0 UBRR Error UBRR Error 207 0.2% 191 0.0% 103 0.2% 95 0.0% 51 0.2% 47 0.0% 34 -0. ...
Page 158
... Max 0.5 Mbps 1 Mbps 1. UBRR = 0, Error = 0.0% ATmega8(L) 158 11.0592 f = MHz osc U2X = 0 U2X = 1 Error UBRR Error UBRR -0.1% 287 0.0% 575 0.2% 143 0.0% 287 0.2% 71 0.0% 143 0. ...
Page 159
... Mbps 1.152 Mbps ATmega8( 20.0000 MHz osc U2X = 1 U2X = 0 UBRR Error UBRR Error 959 0.0% 520 0.0% 479 0.0% 259 0.2% 239 0.0% 129 0.2% 159 ...
Page 160
... Two-wire Serial Interface Features Two-wire Serial Interface Bus Definition TWI Terminology ATmega8(L) 160 • Simple Yet Powerful and Flexible Communication Interface, only two Bus Lines Needed • Both Master and Slave Operation Supported • Device can Operate as Transmitter or Receiver • 7-bit Address Space Allows up to 128 Different Slave Addresses • ...
Page 161
... START behavior, and therefore START is used to describe both START and REPEATED START for the remainder of this datasheet, unless otherwise noted. As depicted below, START and STOP conditions are signalled by changing the level of the SDA line when the SCL line is high. ATmega8(L) Data Stable Data Change 161 ...
Page 162
... Address Packet Format ATmega8(L) 162 Figure 70. START, REPEATED START and STOP conditions SDA SCL START All address packets transmitted on the TWI bus are 9 bits long, consisting of 7 address bits, one READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read operation performed, otherwise a write operation should be per- formed ...
Page 163
... Figure 73 shows a typical data transmission. Note that several data bytes can be trans- mitted between the SLA+R/W and the STOP condition, depending on the software protocol implemented by the application software. Addr LSB R/W ACK Data MSB ATmega8(L) Data LSB ACK Data Byte Data LSB ACK 1 ...
Page 164
... Multi-master Bus Systems, Arbitration and Synchronization ATmega8(L) 164 The TWI protocol allows bus systems with several masters. Special concerns have been taken in order to ensure that transmissions will proceed as normal, even if two or more masters initiate a transmission at the same time. Two problems arise in multi-mas- ter systems: • ...
Page 165
... This implies that in multi-master systems, all data transfers must use the same composition of SLA+R/W and data packets. In other words: All transmissions must contain the same number of data packets, otherwise the result of the arbitration is undefined. ATmega8(L) Master A Loses Arbitration, SDA SDA ...
Page 166
... Overview of the TWI Module SCL and SDA Pins ATmega8(L) 166 The TWI module is comprised of several submodules, as shown in Figure 76. All regis- ters drawn in a thick line are accessible through the AVR data bus. Figure 76. Overview of the TWI Module SCL Spike Slew-rate Control ...
Page 167
... TWI bus, the TWI Interrupt Flag (TWINT) is asserted. In the next clock cycle, the TWI Status Register (TWSR) is updated with a status code identify- ing the event. The TWSR only contains relevant status information when the TWI ATmega8(L) CPU Clock frequency = ...
Page 168
... TWI Register Description TWI Bit Rate Register – TWBR TWI Control Register – TWCR ATmega8(L) 168 Interrupt Flag is asserted. At all other times, the TWSR contains a special status code indicating that no relevant status information is available. As long as the TWINT Flag is set, the SCL line is held low. This allows the application software to complete its tasks before allowing the TWI transmission to continue ...
Page 169
... This bit is a reserved bit and will always read as zero. • Bit 0 – TWIE: TWI Interrupt Enable When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be activated for as long as the TWINT Flag is high. ATmega8(L) 169 ...
Page 170
... TWI Status Register – TWSR TWI Data Register – TWDR TWI (Slave) Address Register – TWAR ATmega8(L) 170 Bit TWS7 TWS6 TWS5 Read/Write Initial Value • Bits 7..3 – TWS: TWI Status These 5 bits reflect the status of the TWI logic and the Two-wire Serial Bus. The differ- ent status codes are described later in this section ...
Page 171
... Figure simple example of how the application can interface to the TWI hardware. In this example, a Master wishes to transmit a single data byte to a Slave. This descrip- tion is quite abstract, a more detailed explanation follows later in this section. A simple code example implementing the desired behavior is also presented. ATmega8(L) TWA3 TWA2 TWA1 ...
Page 172
... TWSTA is written to zero. TWI bus START 2. TWINT set. Status code indicates START condition sent ATmega8(L) 172 5. Check TWSR to see if SLA+W was sent and ACK received. Application loads data into TWDR, and loads appropriate control signals into TWCR, making sure that TWINT is ...
Page 173
... Writing a one to TWINT clears the flag. The TWI will then commence executing whatever operation was specified by the TWCR setting. In the following an assembly and C implementation of the example is given. Note that the code below assumes that several definitions have been made, for example by using include-files. ATmega8(L) 173 ...
Page 174
... MT_DATA_ACK cpi brne ERROR ldi r16, (1<<TWINT)|(1<<TWEN)| (1<<TWSTO) out TWCR, r16 ATmega8(L) 174 C Example TWCR = (1<<TWINT)|(1<<TWSTA)| (1<<TWEN) while (!(TWCR & (1<<TWINT))) ; if ((TWSR & 0xF8) != START) ERROR(); TWDR = SLA_W; ...
Page 175
... When the TWINT Flag is set, the status code in TWSR is used to determine the appro- priate software action. For each status code, the required software action and details of the following serial transfer are given in Table 66 to Table 69. Note that the prescaler bits are masked to zero in these tables. ATmega8(L) 175 ...
Page 176
... Master Transmitter Mode ATmega8(L) 176 In the Master Transmitter mode, a number of data bytes are transmitted to a Slave Receiver (see Figure 78). In order to enter a Master mode, a START condition must be transmitted. The format of the following address packet determines whether Master Transmitter or Master Receiver mode entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered ...
Page 177
... No TWDR action 1 1 Load data byte TWDR action TWDR action TWDR action TWDR action TWDR action 1 0 ATmega8(L) TWSTO TWWC TWEN TWSTO TWWC TWEN TWINT TWEA Next Action Taken by TWI Hardware 1 X SLA+W will be transmitted; ACK or NOT ACK will be received ...
Page 178
... ATmega8(L) 178 Figure 79. Formats and States in the Master Transmitter Mode MT Successfull S SLA W transmission to a slave receiver $08 Next transfer started with a repeated start condition Not acknowledge received after the slave address Not acknowledge received after a data byte Arbitration lost in slave address or data byte ...
Page 179
... STOP condition or a repeated START condition. A STOP condition is generated by writing the following value to TWCR: TWCR TWINT TWEA TWSTA value REPEATED START condition is generated by writing the following value to TWCR: TWCR TWINT TWEA TWSTA value 1 X ATmega8( Device 3 ........ Device n R1 TWSTO TWWC TWEN TWSTO TWWC TWEN ...
Page 180
... ACK has been returned 0x58 Data byte has been received; NOT ACK has been returned ATmega8(L) 180 After a repeated START condition (state 0x10) the Two-wire Serial Interface can access the same Slave again new Slave without transmitting a STOP condition. Repeated START enables the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode without losing control over the bus ...
Page 181
... Figure 82. Data transfer in Slave Receiver mode Device 1 Device 2 SLAVE MASTER RECEIVER TRANSMITTER SDA SCL To initiate the Slave Receiver mode, TWAR and TWCR must be initialized as follows: TWAR TWA6 TWA5 value ATmega8(L) DATA A DATA A $50 $58 P Other master Other master A continues continues $38 Other master ...
Page 182
... ATmega8(L) 182 The upper 7 bits are the address to which the Two-wire Serial Interface will respond when addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address. TWCR TWINT TWEA ...
Page 183
... ATmega8(L) TWEA Next Action Taken by TWI Hardware 0 Data byte will be received and NOT ACK will be returned 1 Data byte will be received and ACK will be returned 0 Data byte will be received and NOT ACK will be returned 1 Data byte will be received and ACK will be returned ...
Page 184
... ATmega8(L) 184 Figure 83. Formats and States in the Slave Receiver Mode Reception of the own S SLA W slave address and one or more data bytes. All are acknowledged Last data byte received is not acknowledged Arbitration lost as master and addressed as slave Reception of the general call General Call ...
Page 185
... While TWEA is zero, the TWI does not respond to its own slave address. However, the Two-wire Serial Bus is still monitored and address recognition may resume at any time by setting TWEA. This implies that the TWEA bit may be used to temporarily isolate the TWI from the Two-wire Serial Bus. ATmega8( ........ ...
Page 186
... Last data byte in TWDR has been transmitted (TWEA = “0”); ACK has been received ATmega8(L) 186 In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA bit is set, the interface can still acknowledge its own slave address or the general call address by using the Two-wire Serial Bus clock as a clock source ...
Page 187
... TWSTO Flag (no other bits in TWCR are affected). The SDA and SCL lines are released, and no STOP condition is transmitted. Application Software Response To TWCR To/from TWDR STA STO No TWDR action No TWCR action No TWDR action 0 1 ATmega8(L) A DATA A DATA $A8 $B8 A $B0 Any number of data bytes A and their associated acknowledge bits ...
Page 188
... Combining Several TWI Modes Multi-master Systems and Arbitration ATmega8(L) 188 In some cases, several TWI modes must be combined in order to complete the desired action. Consider for example reading data from a serial EEPROM. Typically, such a transfer involves the following steps: 1. The transfer must be initiated. ...
Page 189
... No Address / General Call received Yes Write Direction Read ATmega8(L) Data Arbitration lost in Data 38 TWI bus will be released and not addressed slave mode will be entered A START condition will be transmitted when the bus becomes free 68/78 Data byte will be received and NOT ACK will be returned ...
Page 190
... Analog Comparator Special Function IO Register – SFIOR ATmega8(L) 190 The Analog Comparator compares the input values on the positive pin AIN0 and nega- tive pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator Output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function ...
Page 191
... The different settings are shown in Table 71. Table 71. ACIS1/ACIS0 Settings ACIS1 ACIS0 Interrupt Mode 0 0 Comparator Interrupt on Output Toggle 0 1 Reserved 1 0 Comparator Interrupt on Falling Output Edge 1 1 Comparator Interrupt on Rising Output Edge ATmega8( ACI ACIE ACIC ACIS1 ACIS0 R/W R/W R/W R/W R ...
Page 192
... Analog Comparator Multiplexed Input ATmega8(L) 192 When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be dis- abled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed possible to select any of the ADC7..0 Analog Comparator. The ADC multiplexer is used to select this input, and consequently the ADC must be switched off to utilize this feature ...
Page 193
... Interrupt on ADC Conversion Complete • Sleep Mode Noise Canceler The ATmega8 features a 10-bit successive approximation ADC. The ADC is connected to an 8-channel Analog Multiplexer which allows eight single-ended voltage inputs con- structed from the pins of Port C. The single-ended voltage inputs refer to 0V (GND). ...
Page 194
... ATmega8(L) 194 Figure 90. Analog to Digital Converter Block Schematic Operation 8-BIT DATA BUS ADC MULTIPLEXER SELECT (ADMUX) MUX DECODER AVCC INTERNAL 2.56V REFERENCE AREF GND BANDGAP REFERENCE ADC7 ADC6 INPUT ADC5 MUX ADC4 ADC3 ADC2 ADC1 ADC0 The ADC converts an analog input voltage to a 10-bit digital value through successive approximation ...
Page 195
... ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low. When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the con- version starts at the following rising edge of the ADC clock cycle. A normal conversion ATmega8(L) Reset 7-BIT ADC PRESCALER ADC CLOCK SOURCE ...
Page 196
... ATmega8(L) 196 takes 13 ADC clock cycles. The first conversion after the ADC is switched on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry. The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conversion and 13.5 ADC clock cycles after the start of an first conversion. When a con- version is complete, the result is written to the ADC Data Registers, and ADIF is set ...
Page 197
... When ADFR or ADEN is cleared. 2. During conversion, minimum one ADC clock cycle after the trigger event. 3. After a conversion, before the Interrupt Flag used as trigger source is cleared. When updating ADMUX in one of these conditions, the new settings will affect the next ADC conversion. ATmega8(L) Next Conversion ...
Page 198
... ADC Input Channels ADC Voltage Reference ADC Noise Canceler ATmega8(L) 198 When changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: In Single Conversion mode, always select the channel before starting the conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. ...
Page 199
... If any ADC [3..0] port pins are used as digital outputs essential that these do not switch while a conversion is in progress. However, using the Two-wire Interface (ADC4 and ADC5) will only affect the conversion on ADC4 and ADC5 and not the other ADC channels. ATmega8(L) /2) should not be present for ADC 1..100 kΩ ...
Page 200
... ADC Accuracy Definitions ATmega8(L) 200 Figure 96. ADC Power Connections An n-bit single-ended ADC converts a voltage linearly between GND and V steps (LSBs). The lowest code is read as 0, and the highest code is read as 2 Several parameters describe the deviation from the ideal behavior: • ...