PIC18F45J10-I/PT Microchip Technology, PIC18F45J10-I/PT Datasheet - Page 5

• Manufacturer Part Number: PIC18F45J10-I/PT
• Description: IC PIC MCU FLASH 16KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F45J10-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 32
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 32
• Ram Memory Size: 1KB
• Cpu Speed: 40MHz
• No. Of Timers: 3
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1024 B
• Interface Type: MSSP, SPI, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 100 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM163022, DM183040
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180013 - MODULE PLUG-IN 18F45J10 44TQFPAC162067 - HEADER INTRFC MPLAB ICD2 40/28PAC164330 - MODULE SKT FOR 44TQFP 18F45J10
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

9. Module: EUSART
 2009 Microchip Technology Inc.
In rare situations, one or more extra zero bytes
have been observed in a packet transmitted by
the module operating in Asynchronous mode.
The actual data is not lost or corrupted; only
unwanted (extra) zero bytes are observed in the
packet.
This situation has only been observed when the
contents of the Transmit Buffer (TXREG) are
transferred to the TSR during the transmission
of a Stop bit. For this to occur, three things must
happen in the same instruction cycle:
• TXREG is written to
• The baud rate counter overflows (at the end of
• A Stop bit is being transmitted (shifted out of
Work around
If possible, do not use the module’s double-
buffer capability. Instead, load the TXREG
register when the TRMT bit (TXSTA<1>) is set,
indicating the TSR is empty.
If double-buffering is used and back-to-back
transmission is performed, load TXREG imme-
diately after TXIF is set or wait 1 bit time after
TXIF is set. Both solutions prevent writing
TXREG while a Stop bit is transmitted.
The TXIF bit is set at the beginning of the Stop
bit transmission.
If transmission is intermittent, do one of the
following:
• Wait for the TRMT bit to be set before
• Use a free timer resource to time the baud
Affected Silicon Revisions
A2
the bit period)
TSR)
loading TXREG
period:
1.
2.
Do not load the TXREG when the timer is
about to overflow.
X
Set up the timer to overflow at the end of
the Stop bit.
Start the timer when you load the TXREG.
A3
X
A4
X
PIC18F45J10 FAMILY
10. Module: ECCP (Enhanced PWM)
11. Module: MSSP – I
When switching direction in Full-Bridge PWM
mode, the modulated outputs will switch imme-
diately instead of waiting for the next PWM
cycle. This may generate unexpected short
pulses on the modulated outputs.
Work around
Disable the PWM or set the duty cycle to zero
prior to switching directions.
Affected Silicon Revisions
When configured for I
MSSP module may not receive the correct data,
in extremely rare cases. This occurs only if the
Serial
(SSPBUF) is not read within a window after the
SSPIF interrupt (PIR1<3>) has occurred.
Work around
The issue can be resolved in either of these
ways:
• Prior to the I
• Each time the SSPxIF is set, read the
Affected Silicon Revisions
A2
A2
clock stretching feature.
This
(SSPCON2<0>).
SSPBUF before the first rising clock edge of
the next byte being received.
X
X
A3
A3
X
X
is
Receive/Transmit
done
A4
A4
2
X
X
C slave reception, enable the
by
2
C™
2
C slave reception, the
setting
Buffer
DS80494B-page 5
the
register
SEN
bit