PIC16F723A-I/SS Microchip Technology, PIC16F723A-I/SS Datasheet - Page 173
PIC16F723A-I/SS
Manufacturer Part Number
PIC16F723A-I/SS
Description
MCU PIC 3.5K FLASH XLP 28-SSOP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Specifications of PIC16F723A-I/SS
Core Size
8-Bit
Program Memory Size
7KB (4K x 14)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Number Of I /o
25
Program Memory Type
FLASH
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Controller Family/series
PIC16F
No. Of I/o's
25
Ram Memory Size
192Byte
Cpu Speed
20MHz
No. Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
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17.2.10
When the CKP bit is cleared, the SCL output is held low
once it is sampled low. Therefore, the CKP bit will not
stretch the SCL line until an external I
has already asserted the SCL line low. The SCL output
will remain low until the CKP bit is set and all other
devices on the I
ensures that a write to the CKP bit will not violate the
minimum high time requirement for SCL (Figure 17-14).
FIGURE 17-14:
2010 Microchip Technology Inc.
SSPCON
SDA
CKP
SCL
WR
CLOCK SYNCHRONIZATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
2
C bus have released SCL. This
CLOCK SYNCHRONIZATION TIMING
DX
2
C master device
Master device
asserts clock
PIC16F/LF722A/723A
17.2.11
While in Sleep mode, the I
addresses of data, and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if SSP interrupt is enabled).
Master device
deasserts clock
SLEEP OPERATION
2
C module can receive
DS41417A-page 173
DX-1
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