MCIMX512CJM6C Freescale Semiconductor, MCIMX512CJM6C Datasheet - Page 78

• Manufacturer Part Number: MCIMX512CJM6C
• Description: MULTIMEDIA PROC 529-LFBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX51r

Specifications of MCIMX512CJM6C

• Core Processor: ARM Cortex-A8
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: 1-Wire, EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 128
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.8 V ~ 1.15 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 529-LFBGA
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Processor Series: i.MX51
• Core: ARM Cortex A8
• Data Bus Width: 32 bit
• Program Memory Size: 36 KB
• Data Ram Size: 128 KB
• Interface Type: I2C, SPI, SSI, UART, USB
• Maximum Clock Frequency: 200 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 0.8 V to 1.15 V
• Maximum Operating Temperature: + 95 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: MCIMX51EVKJ
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Electrical Characteristics
4.7.4.3
Table 72
input timings listed in
1
4.7.4.4
Table 73
timings listed in
with the IEEE 802.3 MII specification. However the FEC can function correctly with a maximum MDC
frequency of 15 MHz.
78
M10 FEC_MDC falling edge to FEC_MDIO output invalid (minimum propagation delay)
M12 FEC_MDIO (input) to FEC_MDC rising edge setup
M13 FEC_MDIO (input) to FEC_MDC rising edge hold
M14 FEC_MDC pulse width high
M15 FEC_MDC pulse width low
M11 FEC_MDC falling edge to FEC_MDIO output valid (max propagation delay)
.
ID
FEC_COL has the same timing in 10 Mbit 7-wire interface mode.
Num
M9
1
lists MII serial management channel timings.
lists MII asynchronous inputs signal timing information.
FEC_CRS, FEC_COL
MII Async Inputs Signal Timing (FEC_CRS and FEC_COL)
MII Serial Management Channel Timing (FEC_MDIO and FEC_MDC)
FEC_CRS to FEC_COL minimum pulse width
Table
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4
Table
73. The MDC frequency should be equal to or less than 2.5 MHz to be compliant
72.
Characteristic
Figure 44. MII Async Inputs Timing Diagram
Table 72. MII Async Inputs Signal Timing
Table 73. MII Transmit Signal Timing
Characteristic
Figure 45
M9
Min
shows MII serial management channel
1.5
Figure 44
Max
—
shows MII asynchronous
40% 60% FEC_MDC period
40% 60% FEC_MDC period
Min Max
18
—
0
0
FEC_TX_CLK period
Freescale Semiconductor
—
—
—
5
Unit
Unit
ns
ns
ns
ns