MCIMX513DJM8C Freescale Semiconductor, MCIMX513DJM8C Datasheet - Page 67

• Manufacturer Part Number: MCIMX513DJM8C
• Description: MULTIMEDIA PROC 529-LFBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX51r

Specifications of MCIMX513DJM8C

• Core Processor: ARM Cortex-A8
• Core Size: 32-Bit
• Speed: 800MHz
• Connectivity: 1-Wire, EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 128
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.8 V ~ 1.15 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 529-LFBGA
• Processor Series: i.MX51
• Core: ARM Cortex A8
• Data Bus Width: 32 bit
• Program Memory Size: 36 KB
• Data Ram Size: 128 KB
• Interface Type: I2C, SPI, SSI, UART, USB
• Maximum Clock Frequency: 200 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 0.8 V to 1.15 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: MCIMX51EVKJ
• Minimum Operating Temperature: - 20 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
1
2
1
Command /
Slew Rate
Test conditions are: Capacitance 15 pF for DDR contacts. Recommended drive strengths: Medium for SDCLK and High for
address and controls.
SDCLK and DQS related parameters are measured from the 50% point. For example, a high is defined as 50% of the signal
value and a low is defined as 50% of the signal value. DDR SDRAM CLK parameters are measured at the crossing point of
SDCLK and SDCLK_B
These values are for command/address slew rates of 1 V/ns and SDCLK / SDCLK_B differential slew rate of 2 V/ns. For
different values use the settings shown in
Address
DDR6
DDR7
(V/ns)
0.25
0.15
ID
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
Address output setup time
Address output hold time
–1450
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4
+187
+179
+167
+150
+125
–175
–285
–350
–525
–800
Δ
–110
+83
–25
–43
–67
–11
+0
tlS
Table 58. DDR2 SDRAM Timing Parameter Table (continued)
2.0 V/ns
Table 59.
Parameter
–1125
Δ
–125
–188
–292
–375
–500
–708
+94
+89
+83
+75
+45
+21
–14
–31
–54
–83
+0
tlH
Derating Values for DDR2-400 (SDCLK = 200 MHz)
SDCLK Differential Slew Rates
Table
59.
–1420
+217
+209
+197
+180
+155
Δ
+113
–145
–255
–320
–495
–770
+30
+19
–13
–37
–80
+5
tlS
1.5 V/ns
–1095
+124
+105
–158
–262
–345
–470
–678
Δ
+119
+113
+75
+51
+30
+16
–24
–53
–95
–1
tlH
Symbol
t
t
IS
IH
1
1
1,2
–1390
+247
+239
+227
+210
+185
+143
–225
–290
–465
–740
Δ
–115
+60
+49
+35
+17
–50
–7
tlS
SDCLK = 200 MHz
0.475
1.0 V/ns
0.35
Min
–1065
Electrical Characteristics
+154
+149
+143
+135
+105
–128
–232
–315
–440
–648
Δ
+81
+60
+46
+29
–23
–65
+6
tlH
Max
—
—
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
Unit
ns
ns
67