C8051F504-IM Silicon Laboratories Inc, C8051F504-IM Datasheet - Page 103

• Manufacturer Part Number: C8051F504-IM
• Description: IC 8051 MCU 32K FLASH 48-QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F50xr

Specifications of C8051F504-IM

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-QFN
• Mfg Application Notes: LIN Bootloader AppNote
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), CAN, LIN, SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 40
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.25 V
• Data Converters: A/D 32x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: C8051F5x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F500DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 32-ch x 12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1527 - KIT DEV FOR C8051F50X
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1519-5

C8051F50x/F51x
SFR Page 0xC
Automatically
pushed on stack in
SFRPAGE on CAN0
interrupt
0xC
SFRPAGE
(CAN0)
SFRPAGE
pushed to
0x0
SFRNEXT
SFRNEXT
(SPI0DAT)
SFRLAST
Figure 13.3. SFR Page Stack After CAN0 Interrupt Occurs
While in the CAN0 ISR, a PCA interrupt occurs. Recall the PCA interrupt is configured as a high priority
interrupt, while the CAN0 interrupt is configured as a low priority interrupt. Thus, the CIP-51 will now vector
to the high priority PCA ISR. Upon doing so, the CIP-51 will automatically place the SFR page needed to
access the PCA’s special function registers into the SFRPAGE register, SFR Page 0x00. The value that
was in the SFRPAGE register before the PCA interrupt (SFR Page 0x0C for CAN0) is pushed down the
stack into SFRNEXT. Likewise, the value that was in the SFRNEXT register before the PCA interrupt (in
this case SFR Page 0x00 for SPI0DAT) is pushed down to the SFRLAST register, the “bottom” of the
stack. Note that a value stored in SFRLAST (via a previous software write to the SFRLAST register) will be
overwritten. See Figure 13.4.
Rev. 1.2
103