PIC18LF2523-I/SP Microchip Technology, PIC18LF2523-I/SP Datasheet

IC PIC MCU FLASH 16KX16 28-DIP

PIC18LF2523-I/SP

Manufacturer Part Number
PIC18LF2523-I/SP
Description
IC PIC MCU FLASH 16KX16 28-DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18LF2523-I/SP

Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
25
Eeprom Memory Size
256Byte
Ram Memory Size
1.5KB
Cpu Speed
40MHz
No. Of Timers
4
Package
28SPDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Operating Supply Voltage
2.5|3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
25
Interface Type
I2C/SPI/USART
On-chip Adc
10-chx12-bit
Number Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
PIC18F2423/2523/4423/4523
Data Sheet
28/40/44-Pin, Enhanced Flash
Microcontrollers with 12-Bit A/D
and nanoWatt Technology
Preliminary
© 2007 Microchip Technology Inc.
DS39755B

Related parts for PIC18LF2523-I/SP

PIC18LF2523-I/SP Summary of contents

Page 1

... PIC18F2423/2523/4423/4523 Microcontrollers with 12-Bit A/D © 2007 Microchip Technology Inc. 28/40/44-Pin, Enhanced Flash and nanoWatt Technology Preliminary Data Sheet DS39755B ...

Page 2

... Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

Page 3

... PIC18F4423 16K 8192 PIC18F4523 32K 16384 © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Flexible Oscillator Structure: • Four Crystal modes MHz • 4x Phase Lock Loop (available for crystal and internal oscillators) • Two External RC modes MHz • Two External Clock modes MHz • ...

Page 4

... I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information. DS39755B-page /RE3 REF REF (3) 9 /RA7 20 (3) 19 /RA6 ( -/CV 1 REF 21 + REF PIC18F2423 PIC18F2523 (3) /RA7 6 16 (3) /RA6 Preliminary RB7/KBI3/PGD RB6//KBI2/PGC RB5/KBI1/PGM RB4/KBI0/AN11 (2) RB3/AN9/CCP2 RB2/INT2/AN8 RB1/INT1/AN10 RB0/INT0/FLT0/AN12 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA (2) RB3/AN9/CCP2 RB2/INT2/AN8 RB1/INT1/AN10 RB0/INT0/FLT0/AN12 RC7/RX/ © 2007 Microchip Technology Inc. ...

Page 5

... RB3 is the alternate pin for CCP2 multiplexing. 2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 /RE3 1 ...

Page 6

... OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information. DS39755B-page 4 OSC2/CLKO OSC1/CLKI PIC18F4423 PIC18F4523 RE2/CS/AN7 27 7 RE1/WR/AN6 8 26 RE0/RD/AN5 9 25 RA5/AN4/SS/HLVDIN/C2OUT RA4/T0CKI/C1OUT 11 SS Preliminary (3) /RA6 (3) /RA7 . © 2007 Microchip Technology Inc. ...

Page 7

... Appendix E: Migration from Mid-Range to Enhanced Devices .......................................................................................................... 375 Appendix F: Migration from High-End to Enhanced Devices ............................................................................................................. 375 Index ................................................................................................................................................................................................. 377 The Microchip Web Site ..................................................................................................................................................................... 387 Customer Change Notification Service .............................................................................................................................................. 387 Customer Support .............................................................................................................................................................................. 387 Reader Response .............................................................................................................................................................................. 388 PIC18F2423/2523/4423/4523 Product Identification System ............................................................................................................ 389 © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Preliminary DS39755B-page 5 ...

Page 8

... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39755B-page 6 Preliminary © 2007 Microchip Technology Inc. ...

Page 9

... Low Consumption in Key Modules: The power requirements for both Timer1 and the Watchdog Timer are minimized. See Section 26.0 “Electrical Characteristics” for values. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18LF2423/2523/4423/4523 ...

Page 10

... Figure 1-2. The devices are differentiated from each other in five ways: 1. Flash program memory PIC18LF2423/4423 devices and 32 Kbytes for PIC18LF2523/4523). 2. A/D channels (10 for 28-pin devices, 13 for 40/44-pin devices). 3. I/O ports (3 bidirectional ports on 28-pin devices, 5 bidirectional ports on 40/44-pin devices). 4. CCP and Enhanced CCP implementation ...

Page 11

... MCLR (optional), WDT Programmable High/Low-Voltage Detect Programmable Brown-out Reset Instruction Set 75 Instructions; 83 with Extended Instruction Set enabled Packages 28-pin PDIP 28-pin SOIC 28-pin QFN © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 PIC18F2523 DC – 40 MHz 16384 32768 8192 16384 768 1536 256 256 ...

Page 12

... Preliminary PORTA RA0/AN0 RA1/AN1 RA2/AN2/V -/CV REF REF RA3/AN3/V + REF RA4/T0CKI/C1OUT RA5/AN4/SS/HLVDIN/C2OUT (3) OSC2/CLKO /RA6 (3) OSC1/CLKI /RA7 PORTB RB0/INT0/FLT0/AN12 RB1/INT1/AN10 RB2/INT2/AN8 (1) RB3/AN9/CCP2 RB4/KBI0/AN11 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD PORTC RC0/T1OSO/T13CKI (1) RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT PORTE (2) MCLR/V /RE3 PP © 2007 Microchip Technology Inc. ...

Page 13

... RE3 is only available when MCLR functionality is disabled. 3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Data Latch 8 Data Memory ( 3 ...

Page 14

... Crystal Oscillator mode. O — mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. I/O TTL General purpose I/O pin. CMOS = CMOS compatible input or output I = Input P = Power Preliminary Description © 2007 Microchip Technology Inc. ...

Page 15

... Schmitt Trigger input with CMOS levels O = Output Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Pin Buffer Type Type PORTA is a bidirectional I/O port. ...

Page 16

... Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming clock pin. I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output I = Input P = Power Preliminary Description © 2007 Microchip Technology Inc. ...

Page 17

... Schmitt Trigger input with CMOS levels O = Output Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Pin Buffer Type Type PORTC is a bidirectional I/O port. ...

Page 18

... Crystal Oscillator mode. O — mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. I/O TTL General purpose I/O pin. CMOS = CMOS compatible input or output I = Input P = Power Preliminary Description © 2007 Microchip Technology Inc. ...

Page 19

... Schmitt Trigger input with CMOS levels O = Output Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Pin Buffer Type Type PORTA is a bidirectional I/O port. ...

Page 20

... Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming clock pin. 17 I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output I = Input P = Power Preliminary Description © 2007 Microchip Technology Inc. ...

Page 21

... Schmitt Trigger input with CMOS levels O = Output Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Pin Buffer Type Type PORTC is a bidirectional I/O port. ...

Page 22

... Enhanced CCP1 output. 4 I/O ST Digital I/O. I/O TTL Parallel Slave Port data. O — Enhanced CCP1 output. 5 I/O ST Digital I/O. I/O TTL Parallel Slave Port data. O — Enhanced CCP1 output. CMOS = CMOS compatible input or output I = Input P = Power Preliminary Description © 2007 Microchip Technology Inc. ...

Page 23

... Schmitt Trigger input with CMOS levels O = Output Note 1: Default assignment for CCP2 when Configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Pin Buffer Type Type PORTE is a bidirectional I/O port. ...

Page 24

... PIC18F2423/2523/4423/4523 NOTES: DS39755B-page 22 Preliminary © 2007 Microchip Technology Inc. ...

Page 25

... The oscillator design requires the use of a parallel cut crystal. Note: Use of a series cut crystal may give a fre- quency out of the crystal manufacturer’s specifications. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 FIGURE 2-1: (1) C1 (1) C2 Note 1: See Table 2-1 and Table 2-2 for initial values of C1 and C2 ...

Page 26

... Clock from Ext. System Preliminary EXTERNAL CLOCK INPUT OPERATION (HS OSC. CONFIGURATION) OSC1 PIC18FXXXX (HS Mode) OSC2 Open EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION) OSC1/CLKI PIC18FXXXX /4 OSC2/CLKO OSC EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION) OSC1/CLKI PIC18FXXXX RA6 I/O (OSC2) © 2007 Microchip Technology Inc. ...

Page 27

... Recommended values: 5K ≤ R ≤ 100 kΩ EXT C > EXT © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 2.5 PLL Frequency Multiplier A Phase Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower frequency oscillator circuit clock the device up to its highest rated frequency from a crystal oscillator ...

Page 28

... Three compensation techniques are discussed in Section 2.6.5.1 EUSART”, Section 2.6.5.2 “Compensating with the Timers” and Section 2.6.5.3 “Compensating with the CCP Module in Capture Mode”, but other techniques may be used. Preliminary or temperature changes, which can “Compensating with the © 2007 Microchip Technology Inc. ...

Page 29

... If the internally clocked timer value is greater than expected, then the internal oscillator block is running too fast. To adjust for this, decrement the OSCTUNE register. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 R/W-0 R/W-0 R/W-0 ...

Page 30

... OSCTUNE<7> Preliminary devices offer the are shown in Figure 2-8. See LP, XT, HS, RC, EC Peripherals T1OSC Internal Oscillator CPU IDLEN Clock Control FOSC3:FOSC0 OSCCON<1:0> Clock Source Option for other Modules WDT, PWRT, FSCM and Two-Speed Start-up © 2007 Microchip Technology Inc. ...

Page 31

... If none of these bits are set, the INTRC is providing the clock or INTOSC has just started and is not yet stable. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 The IDLEN bit determines if the device goes into Sleep mode or one of the Idle modes when the SLEEP instruction is executed ...

Page 32

... Source selected by the INTSRC bit (OSCTUNE<7>), see text. 3: Default output frequency of INTOSC on Reset. DS39755B-page 30 (1) R/W-0 R R-0 IRCF0 OSTS IOFS U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) (1) Preliminary R/W-0 R/W-0 SCS1 SCS0 bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 33

... Feedback inverter disabled at quiescent voltage level Note: See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 not require a device clock source (i.e., MSSP slave, PSP, INTn pins and others). Peripherals that may add ...

Page 34

... PIC18F2423/2523/4423/4523 NOTES: DS39755B-page 32 Preliminary © 2007 Microchip Technology Inc. ...

Page 35

... Note 1: IDLEN reflects its value when the SLEEP instruction is executed. 2: Includes INTOSC and INTOSC postscaler, as well as the INTRC source. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 3.1.1 CLOCK SOURCES The SCS1:SCS0 bits allow the selection of one of three clock sources for power-managed modes. They are: • ...

Page 36

... When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run. Preliminary © 2007 Microchip Technology Inc. ...

Page 37

... PRI_RUN RC_RUN modes during execution. However, a clock switch delay will occur during entry to and exit from RC_RUN mode. Therefore, if the primary clock source is the internal oscillator block, the use of RC_RUN mode is not recommended. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 n-1 n ...

Page 38

... The IDLEN and SCS bits are not affected by the switch. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled n-1 n (1) Clock Transition OSC (1) PLL ( n-1 n Clock (2) Transition OSTS bit Set . OSC Preliminary © 2007 Microchip Technology Inc. ...

Page 39

... (approx). These intervals are not shown to scale. OST OSC PLL © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 3.4 Idle Modes The Idle modes allow the controller’s CPU to be shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to a ‘ ...

Page 40

... SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled but not yet running, peripheral clocks will be delayed until the oscillator has started. In such sit- uations, initial oscillator operation is far from stable and unpredictable operation may result CSD PC Preliminary © 2007 Microchip Technology Inc. ...

Page 41

... INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 On all exits from Idle or Sleep modes by interrupt, code execution branches to the interrupt vector if the GIE/ GIEH bit (INTCON< ...

Page 42

... LP, XT OST HSPLL T OST EC CSD (1) INTOSC T IOBST is the PLL Lock-out Timer (parameter F12 (parameter 39), the INTOSC stabilization period. IOBST Preliminary Clock Ready Status Bit (OSCCON) OSTS (1) IOFS (3) ( OSTS rc (1) (4) IOFS (4) ( OSTS rc (1) IOFS (3) ( OSTS rc (1) (4) IOFS © 2007 Microchip Technology Inc. ...

Page 43

... Ripple Counter Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin. 2: See Table 4-2 for time-out situations. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 A simplified block diagram of the on-chip Reset circuit is shown in Figure 4-1. ...

Page 44

... Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after POR). DS39755B-page 42 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) Preliminary (2) R/W-0 R/W-0 POR BOR bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 45

... The state of the bit is set to ‘0’ whenever a POR occurs; it does not change for any other Reset event. POR is not reset to ‘1’ by any hardware event. To capture multiple events, the user manually resets the bit to ‘1’ in software following any POR. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 FIGURE 4- ...

Page 46

... BOR current. BOR Operation BOR disabled; must be enabled by reprogramming the Configuration bits. BOR enabled in software; operation controlled by SBOREN. BOR enabled in hardware in Run and Idle modes, disabled during Sleep mode. BOR enabled in hardware. Preliminary © 2007 Microchip Technology Inc. ...

Page 47

... INTIO1, INTIO2 66 ms Note (65.5 ms) is the nominal Power-up Timer (PWRT) delay the nominal time required for the PLL to lock. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 4.5.3 PLL LOCK TIME-OUT With the PLL enabled in its PLL mode, the time-out incorporate sequence following a Power-on Reset is slightly differ- ent from other oscillator modes ...

Page 48

... OST TIME-OUT INTERNAL RESET FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR RISES AFTER MCLR INTERNAL POR PWRT TIME-OUT OSC1 OST TIME-OUT INTERNAL RESET DS39755B-page 46 T PWRT T OST T PWRT T OST T PWRT T OST Preliminary © 2007 Microchip Technology Inc RISE < PWRT COMPLETES) OST COMPLETES) OST ...

Page 49

... INTERNAL RESET FIGURE 4-7: TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OSC1 OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 OSC1 cycles. T OST PLL © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 , PWRT T OST T PWRT T OST T PLL ≈ max. ...

Page 50

... Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups. RCON Register Program Counter POR 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h ( Preliminary STKPTR Register BOR STKFUL STKUNF © 2007 Microchip Technology Inc. ...

Page 51

... See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 MCLR Resets, Power-on Reset, ...

Page 52

... Microchip Technology Inc. ...

Page 53

... See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 MCLR Resets, Power-on Reset, ...

Page 54

... Microchip Technology Inc. ...

Page 55

... High Priority Interrupt Vector Low Priority Interrupt Vector On-Chip Program Memory PIC18FX423 Read ‘0’ © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 5.1 Program Memory Organization PIC18 microcontrollers implement a 21-bit program counter, which is capable of addressing a 2-Mbyte program memory space. Accessing a location between the upper boundary of the physically implemented memory and the 2-Mbyte address will return all ‘ ...

Page 56

... The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption. Return Address Stack<20:0> 11111 11110 11101 TOSL 34h 00011 001A34h 00010 Top-of-Stack 000D58h 00001 00000 Preliminary Stack Pointer STKPTR<4:0> 00010 © 2007 Microchip Technology Inc. ...

Page 57

... SP4:SP0: Stack Pointer Location bits Note 1: Bit 7 and bit 6 are cleared by user software POR. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero ...

Page 58

... Data is transferred to or from program memory one byte at a time. Table read and table write operations are discussed further in Section 6.1 “Table Reads and Table Writes”. Preliminary nn COMPUTED GOTO USING AN OFFSET VALUE OFFSET, W TABLE PCL nnh nnh nnh © 2007 Microchip Technology Inc. ...

Page 59

... Instruction @ address SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 5.2.2 INSTRUCTION FLOW/PIPELINING An “ ...

Page 60

... REG1 ; is RAM location 0? REG1, REG2 ; Yes, execute this word ; 2nd word of instruction REG3 ; continue code Preliminary 0006h is encoded in the program Word Address ↓ 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h © 2007 Microchip Technology Inc. ...

Page 61

... SFRs and the lower portion of GPR Bank 0 without using the BSR. Section 5.3.2 “Access Bank” provides a detailed description of the Access RAM. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 5.3.1 BANK SELECT REGISTER (BSR) Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible ...

Page 62

... Bank 0). The second 128 bytes are Special Function Registers (from Bank 15). When ‘a’ The BSR specifies the Bank used by the instruction. Access Bank 00h Access RAM Low 7Fh 80h Access RAM High (SFRs) FFh © 2007 Microchip Technology Inc. ...

Page 63

... FIGURE 5-6: DATA MEMORY MAP FOR PIC18LF2523/4523 DEVICES BSR<3:0> 00h = 0000 Bank 0 FFh 00h = 0001 Bank 1 FFh 00h = 0010 Bank 2 FFh 00h = 0011 Bank 3 FFh 00h = 0100 Bank 4 FFh 00h = 0101 Bank 5 FFh 00h = 0110 Bank 6 FFh 00h = 0111 Bank 7 FFh ...

Page 64

... This is data RAM which is available for use by all instructions. GPRs start at the bottom of Bank 0 (address 000h) and grow downwards towards the bot- tom of the SFR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other Resets. Preliminary (2) From Opcode © 2007 Microchip Technology Inc. ...

Page 65

... Unimplemented registers are read as ‘0’. 3: This register is not available on 28-pin devices. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 The SFRs can be classified into two sets: those asso- ciated with the “core” device functionality (ALU, Resets and interrupts) and those related to the peripheral func- tions. The Reset and Interrupt registers are described in their respective chapters, while the ALU’ ...

Page 66

... N/A 50, 69 N/A 50, 69 N/A 50, 69 N/A 50, 69 N/A 50, 69 50, 69 ---- 0000 50, 69 xxxx xxxx C 50, 67 ---x xxxx ‘ ’ . See Section 2.6.4 “PLL in 0 ‘ ’ . This bit is 0 © 2007 Microchip Technology Inc. ...

Page 67

... The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0); otherwise, RE3 reads as read-only. 5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Bit 4 Bit 3 Bit 2 ...

Page 68

... RE0 52, 117 ---- xxxx RD0 52, 114 xxxx xxxx RC0 52, 111 xxxx xxxx RB0 52, 108 xxxx xxxx RA0 52, 105 xx0x 0000 ‘ ’ . See Section 2.6.4 “PLL in 0 ‘ ’ . This bit is 0 © 2007 Microchip Technology Inc. ...

Page 69

... For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 It is recommended that only BCF, BSF, SWAPF, MOVFF ...

Page 70

... Example 5-5. EXAMPLE 5-5: HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING LFSR FSR0, 100h ; NEXT CLRF POSTINC0 BTFSS FSR0H, 1 BRA NEXT CONTINUE Preliminary © 2007 Microchip Technology Inc. ; Clear INDF ; register then ; inc pointer ; All done with ; Bank1? ; NO, clear next ; YES, continue ...

Page 71

... In this case, the FSR1 pair contains ECCh. This means the contents of location ECCh will be added to that of the W register and stored back in ECCh. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 5.4.3.2 FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are “ ...

Page 72

... Figure 5-9. Those who desire to use byte-oriented or bit-oriented instructions in the Indexed Literal Offset mode should note the changes to assembler syntax for this mode. This is described in more detail in Section 24.2.1 “Extended Instruction Syntax”. Preliminary © 2007 Microchip Technology Inc. ...

Page 73

... The bank is designated by the Bank Select Register (BSR). The address can be in any implemented bank in the data memory space. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 000h 060h 080h Bank 0 100h Bank 1 ...

Page 74

... These instructions are executed as described in Section 24.2 “Extended Instruction Set”. Bank 0 Bank 0 Bank 1 Window Bank 1 Bank 2 through Bank 14 Bank 15 SFRs Data Memory Preliminary 00h Bank 1 “Window” 5Fh Bank 0 7Fh 80h SFRs FFh Access Bank © 2007 Microchip Technology Inc. ...

Page 75

... TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 6.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...

Page 76

... The WR control bit initiates write operations. The bit cannot be cleared, only set, in software cleared in hardware at the completion of the write operation. When set, Note: The EEIF interrupt flag bit (PIR2<4>) is set when the write is complete. It must be cleared in software. Preliminary Table Latch (8-bit) TABLAT © 2007 Microchip Technology Inc. ...

Page 77

... RD bit cannot be set when EEPGD = 1 or CFGS = 1 Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 R/W-0 R/W-x R/W-0 ...

Page 78

... Figure 6-3 describes the relevant boundaries of TBLPTR based on Flash program memory operations. Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 Preliminary TBLPTRL 0 © 2007 Microchip Technology Inc. ...

Page 79

... WORD_EVEN TBLRD*+ MOVFW TABLAT, W MOVF WORD_ODD © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...

Page 80

... TBLPTR with the base ; address of the memory block ; point to Flash program memory ; access Flash program memory ; enable write to memory ; enable Row Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts Preliminary © 2007 Microchip Technology Inc. ...

Page 81

... EEPGD bit to point to program memory; • clear the CFGS bit to access program memory; • set WREN to enable byte writes. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 The long write is necessary for programming the inter- nal Flash. Instruction execution is halted while in a long write cycle ...

Page 82

... Flash ; number of bytes in holding register ; get low byte of buffer data ; present data to table latch ; short write to holding ; register using pre-increment ; loop until buffers are full Preliminary © 2007 Microchip Technology Inc. ...

Page 83

... If the write operation is interrupted by a MCLR Reset or a WDT Time-out Reset during normal operation, the user can check the WRERR bit and rewrite the location(s) as needed. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 ; point to Flash program memory ; access Flash program memory ...

Page 84

... Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) INT0IE RBIE TMR0IF — FREE WRERR WREN — EEIP BCLIP HLVDIP — EEIF BCLIF HLVDIF — EEIE BCLIE HLVDIE Preliminary Reset Bit 1 Bit 0 Values on page INT0IF RBIF TMR3IP CCP2IP 52 TMR3IF CCP2IF 52 TMR3IE CCP2IE 52 © 2007 Microchip Technology Inc. ...

Page 85

... EECON1 and EECON2. These are the same registers which control access to the program memory and are used in a similar manner for the data EEPROM. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 The EECON1 register (Register 7-1) is the control register for data and program memory access. Control bit EEPGD determines if the access will be to program Flash or data EEPROM memory ...

Page 86

... When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. DS39755B-page 84 R/W-0 R/W-x R/W-0 (1) FREE WRERR WREN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/S-0 R/S bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 87

... EECON1, WR BSF INTCON, GIE BCF EECON1, WREN © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code exe- cution (i.e., runaway programs). The WREN bit should be kept clear at all times, except when updating the EEPROM ...

Page 88

... Set for Data EEPROM ; Disable interrupts ; Enable writes ; Loop to refresh array ; Read current address ; ; Write 55h ; ; Write 0AAh ; Set WR bit to begin write ; Wait for write to complete ; Increment address ; Not zero again ; Disable writes ; Enable interrupts Preliminary © 2007 Microchip Technology Inc. ...

Page 89

... EEPGD CFGS IPR2 OSCFIP CMIP PIR2 OSCFIF CMIF PIE2 OSCFIE CMIE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE INT0IE RBIE TMR0IF — FREE ...

Page 90

... PIC18F2423/2523/4423/4523 NOTES: DS39755B-page 88 Preliminary © 2007 Microchip Technology Inc. ...

Page 91

... Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 EXAMPLE 8-1: MOVF ARG1, W MULWF ARG2 EXAMPLE 8-2: MOVF ARG1, W MULWF ARG2 ...

Page 92

... PRODL RES1 Add cross PRODH products ; WREG ; ; ARG1H ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL PRODL RES1 Add cross PRODH products ; WREG ; ; ARG2H ARG2H:ARG2L neg? SIGN_ARG1 ; no, check ARG1 ARG1L RES2 ; ARG1H ARG1H ARG1H:ARG1L neg? CONT_CODE ; no, done ARG2L RES2 ; ARG2H © 2007 Microchip Technology Inc. ...

Page 93

... Individual interrupts can be disabled through their corresponding enable bits. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are ...

Page 94

... INT2IE INT2IP IPEN IPEN PEIE/GIEL IPEN TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP Preliminary © 2007 Microchip Technology Inc. Wake- Idle or Sleep modes Interrupt to CPU Vector to Location 0008h GIE/GIEH Interrupt to CPU Vector to Location 0018h GIE/GIEH PEIE/GIEL ...

Page 95

... None of the RB7:RB4 pins have changed state Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Note: Interrupt flag bits are set when an interrupt ...

Page 96

... User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt, otherwise, an interrupt will occur as soon as interrupts are enabled. DS39755B-page 94 R/W-1 U-0 R/W-1 INTEDG2 — TMR0IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 R/W-1 — RBIP bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 97

... This feature allows for software polling. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt, otherwise, an interrupt will occur as soon as interrupts are enabled. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 R/W-0 ...

Page 98

... R-0 R/W-0 R/W-0 TXIF SSPIF CCP1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary © 2007 Microchip Technology Inc. R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown ...

Page 99

... A TMR1 register capture occurred (must be cleared in software TMR1 register capture occurred Compare mode TMR1 register compare match occurred (must be cleared in software TMR1 register compare match occurred PWM mode: Unused in this mode. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 R/W-0 R/W-0 R/W-0 EEIF BCLIF HLVDIF U = Unimplemented bit, read as ‘ ...

Page 100

... Disables the TMR1 overflow interrupt Note 1: This bit is unimplemented on 28-pin devices and will read as ‘0’. DS39755B-page 98 R-0 R/W-0 R/W-0 TXIE SSPIE CCP1IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary © 2007 Microchip Technology Inc. R/W-0 R/W-0 TMR2IE TMR1IE bit Bit is unknown ...

Page 101

... Enabled 0 = Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 R/W-0 R/W-0 R/W-0 EEIE BCLIE HLVDIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary ...

Page 102

... Note 1: This bit is unimplemented on 28-pin devices and will read as ‘0’. DS39755B-page 100 R/W-1 R/W-1 R/W-1 TXIP SSPIP CCP1IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 103

... Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 R/W-1 R/W-1 R/W-1 EEIP BCLIP HLVDIP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...

Page 104

... The operation of the SBOREN bit and the Reset flag bits is discussed in more detail in Section 4.1 “RCON Register”. R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) Preliminary (2) R/W-0 R/W-0 POR BOR bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 105

... MOVFF BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 9.7 TMR0 Interrupt In 8-bit mode (which is the default), an overflow in the TMR0 register (FFh → 00h) will set flag bit, TMR0IF. In 16-bit mode, an overflow in the TMR0H:TMR0L regis- ter pair (FFFFh → 0000h) will set TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE (INTCON< ...

Page 106

... PIC18F2423/2523/4423/4523 NOTES: DS39755B-page 104 Preliminary © 2007 Microchip Technology Inc. ...

Page 107

... Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Reading the PORTA register reads the status of the pins, whereas writing to it, will write to the port latch. ...

Page 108

... PORTA<6> data input. Enabled in RCIO, INTIO2 and ECIO modes only. I ANA Main oscillator input connection. I ANA Main clock input connection. O DIG LATA<7> data output. Disabled in external oscillator modes. I TTL PORTA<7> data input. Disabled in external oscillator modes. Preliminary Description /4) in RC, INTIO1 and EC Oscillator OSC © 2007 Microchip Technology Inc. ...

Page 109

... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Bit 5 Bit 4 ...

Page 110

... RB2:RB0 offer external interrupt inputs (INT2:INT0, respectively). See Section 9.6 “INTn Pin Interrupts” for details. RB0 offers an input (FLT0) for use when ECCP1 is using an external Fault input to disable ECCP1 Faults. See Section 16.4.7 “Enhanced PWM Auto-Shutdown” for details. Preliminary © 2007 Microchip Technology Inc. ...

Page 111

... PBADEN is set and digital inputs when PBADEN is cleared. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is ‘0’. Default assignment is RC1. 3: All other pin functions are disabled when ICSP or ICD are enabled. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 I/O I/O Type ...

Page 112

... Bit 4 Bit 3 Bit 2 RB5 RB4 RB3 RB2 INT0IE RBIE TMR0IF — TMR0IP — INT2IE INT1IE — VCFG1 VCFG0 PCFG3 PCFG2 Preliminary Reset Bit 1 Bit 0 Values on page RB1 RB0 INT0IF RBIF 49 — RBIP 49 INT2IF INT1IF 49 PCFG1 PCFG0 51 © 2007 Microchip Technology Inc. ...

Page 113

... Compare/PWM (CCP) Modules”) depending on the Configuration bit, CCP2MX CONFIG3H). © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input ...

Page 114

... I ST PORTC<7> data input Asynchronous serial receive data input (EUSART module). O DIG Synchronous serial data output (EUSART module); takes priority over port data Synchronous serial data input (EUSART module). User must configure as an input. Preliminary Description © 2007 Microchip Technology Inc. ...

Page 115

... SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Name Bit 7 Bit 6 PORTC RC7 RC6 LATC PORTC Data Latch Register (Read and Write to Data Latch) TRISC PORTC Data Direction Control Register © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Bit 5 Bit 4 Bit 3 Bit 2 RC5 RC4 RC3 RC2 Preliminary ...

Page 116

... EXAMPLE 10-4: INITIALIZING PORTD CLRF PORTD ; Initialize PORTD by ; clearing output ; data latches CLRF LATD ; Alternate method ; to clear output ; data latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISD ; Set RD<3:0> as inputs ; RD<5:4> as outputs ; RD<7:6> as inputs Preliminary © 2007 Microchip Technology Inc. ...

Page 117

... DIG = Digital level output; TTL = TTL input buffer Schmitt Trigger input buffer Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: These registers and/or bits are not implemented on 28-pin devices. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 (1) I/O ...

Page 118

... These registers and/or bits are not implemented on 28-pin devices. DS39755B-page 116 Bit 5 Bit 4 Bit 3 Bit 2 RD5 RD4 RD3 RD2 IBOV PSPMODE — TRISE2 DC1B1 DC1B0 CCP1M3 CCP1M2 Preliminary (1) Reset Bit 1 Bit 0 Values on page RD1 RD0 TRISE1 TRISE0 52 CCP1M1 CCP1M0 51 © 2007 Microchip Technology Inc. ...

Page 119

... The Data Latch register (LATE) is also memory mapped. Read-modify-write operations on the LATE register, read and write the latched output value for PORTE. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 The fourth pin of PORTE (MCLR/V only pin. Its operation is controlled by the MCLRE Con- figuration bit. When selected as a port pin (MCLRE = 0), it functions as a digital input only pin ...

Page 120

... TRISE1: RE1 Direction Control bit 1 = Input 0 = Output bit 0 TRISE0: RE0 Direction Control bit 1 = Input 0 = Output DS39755B-page 118 R/W-0 U-0 R/W-1 PSPMODE — TRISE2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 TRISE1 TRISE0 bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 121

... Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0). 2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are implemented only when PORTE is implemented (i.e., 40/44-pin devices). © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 I/O I/O ...

Page 122

... Set Interrupt Flag PSPIF (PIR1<7>) Note: I/O pins have diode protection to V Preliminary PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT) One bit of PORTD D Q RDx pin CK TTL PORTE Pins Read RD TTL Chip Select CS TTL Write WR TTL and © 2007 Microchip Technology Inc. ...

Page 123

... INTCON GIE/GIEH PEIE/GIEL TMR0IF PIR1 PSPIF ADIF PIE1 PSPIE ADIE IPR1 PSPIP ADIP ADCON1 — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Bit 5 Bit 4 Bit 3 Bit 2 ...

Page 124

... PIC18F2423/2523/4423/4523 NOTES: DS39755B-page 122 Preliminary © 2007 Microchip Technology Inc. ...

Page 125

... Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 The T0CON register (Register 11-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 11-1 ...

Page 126

... Sync with Internal TMR0L Clocks Delay Preliminary ). There is a delay between OSC Set TMR0L TMR0IF on Overflow 8 8 Internal Data Bus Set TMR0 TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 8 Internal Data Bus © 2007 Microchip Technology Inc. ...

Page 127

... TRISA6 Legend: Shaded cells are not used by Timer0. Note 1: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 11.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “ ...

Page 128

... PIC18F2423/2523/4423/4523 NOTES: DS39755B-page 126 Preliminary © 2007 Microchip Technology Inc. ...

Page 129

... OSC bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 A simplified block diagram of the Timer1 module is shown in Figure 12-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 12-2. The module incorporates its own low-power oscillator to provide an additional clocking option ...

Page 130

... Special Event Trigger) 8 Preliminary 1 Synchronize 0 Detect Peripheral Clock Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 1 Synchronize 0 Detect Peripheral Clock Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 TMR1H 8 8 Internal Data Bus © 2007 Microchip Technology Inc. ...

Page 131

... COMPONENTS FOR THE TIMER1 LP OSCILLATOR PIC18FXXXX C1 T1OSI XTAL 32.768 kHz T1OSO C2 Note: See the Notes with Table 12-1 for additional information about capacitor selection. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 TABLE 12-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Osc Type 12.6 pF 6.0 pF) L ...

Page 132

... For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> = 1), as shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. Preliminary © 2007 Microchip Technology Inc. ...

Page 133

... T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Legend: Shaded cells are not used by the Timer1 module. Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ...

Page 134

... PIC18F2423/2523/4423/4523 NOTES: DS39755B-page 132 Preliminary © 2007 Microchip Technology Inc. ...

Page 135

... TMR2ON: Timer2 On bit 1 = Timer2 Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 13.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 4-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by- 16 prescale options ...

Page 136

... Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF TXIF SSPIF CCP1IF TXIE SSPIE CCP1IE TXIP SSPIP CCP1IP Preliminary Set TMR2IF TMR2 Output (to PWM or MSSP) PR2 8 Reset Bit 1 Bit 0 Values on page INT0IF RBIF 49 TMR2IF TMR1IF 52 TMR2IE TMR1IE 52 TMR2IP TMR1IP © 2007 Microchip Technology Inc. ...

Page 137

... OSC bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 A simplified block diagram of the Timer3 module is shown in Figure 14-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 14-2. The Timer3 module is controlled through the T3CON register (Register 14-1) ...

Page 138

... Clear TMR3 TMR3L 8 Preliminary 1 Synchronize 0 Detect Peripheral Clock Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 1 Synchronize 0 Detect Peripheral Clock Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 8 Read TMR3L Write TMR3L 8 TMR3H 8 8 Internal Data Bus © 2007 Microchip Technology Inc. ...

Page 139

... T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 14.4 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h. The Timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, TMR3IF (PIR2< ...

Page 140

... PIC18F2423/2523/4423/4523 NOTES: DS39755B-page 138 Preliminary © 2007 Microchip Technology Inc. ...

Page 141

... CCPx pin reflects I/O state) 1011 = Compare mode: trigger special event, reset timer, start A/D conversion on CCP2 match (CCPxIF bit is set) 11xx = PWM mode © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 The Capture and Compare operations described in this chapter apply to all standard and Enhanced CCP modules ...

Page 142

... Changing the pin assignment of CCP2 does not auto- matically change any requirements for configuring the port pin. Users must always verify that the appropriate TRIS register is configured correctly for CCP2 operation, regardless of where it is located. Interaction Preliminary © 2007 Microchip Technology Inc. ...

Page 143

... CCP1CON<3:0> 4 Q1:Q4 CCP2CON<3:0> CCP2 pin Prescaler ÷ © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 15.2.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit clear while changing the CCP mode to avoid false interrupts. The interrupt flag bit, CCPxIF, should also be cleared following any such change in operating mode ...

Page 144

... Set CCP1IF Output Compare Match Logic 4 CCP1CON<3:0> 0 Special Event Trigger 1 (Timer1/Timer3 Reset, A/D Trigger) T3CCP2 Set CCP2IF Compare Output Match Logic 4 CCP2CON<3:0> Preliminary Special Event Trigger mode CCP1 pin TRIS Output Enable CCP2 pin TRIS Output Enable © 2007 Microchip Technology Inc. ...

Page 145

... These bits are unimplemented on 28-pin devices; always maintain these bits clear. 2: The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Bit 5 Bit 4 ...

Page 146

... CCPRxH until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPRxH is a read-only register. Preliminary • OSC (TMR2 Prescale Value) L:CCP CON<5:4>) • • (TMR2 Prescale Value) OSC © 2007 Microchip Technology Inc. ...

Page 147

... The PWM auto-shutdown features of the Enhanced CCP module are also available to CCP1 in 28-pin devices. The operation of this feature is discussed in detail in Section 16.4.7 “Enhanced PWM Auto-Shutdown”. Auto-shutdown features are not available for CCP2. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 EQUATION 15-3: PWM Resolution (max) = Note: ...

Page 148

... PSSAC1 PSSAC0 PSSBD1 (1) (1) (1) PDC5 PDC4 PDC3 PDC2 Preliminary Reset Bit 2 Bit 1 Bit 0 Values on page INT0IF RBIF 49 PD POR BOR 48 TMR2IF TMR1IF 52 TMR2IE TMR1IE 52 TMR2IP TMR1IP CCP1M1 CCP1M0 CCP2M1 CCP2M0 51 (1) (1) PSSBD0 51 (1) (1) (1) PDC1 PDC0 51 © 2007 Microchip Technology Inc. ...

Page 149

... PWM mode; P1A, P1C active-high; P1B, P1D active-low 1110 = PWM mode; P1A, P1C active-low; P1B, P1D active-high 1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 enhanced features are discussed in detail in Section 16.4 “Enhanced PWM Mode”. Capture, ...

Page 150

... PWM. and Timer RC2 RD5 All 40/44-pin devices: CCP1 RD5/PSP5 P1A P1B P1A P1B Preliminary and Section 15.3 “Compare for PWM Operation” or RD6 RD7 RD6/PSP6 RD7/PSP7 RD6/PSP6 RD7/PSP7 P1C P1D © 2007 Microchip Technology Inc. ...

Page 151

... CCP1 pin and latch D.C. PR2 Note 1: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock bits of the prescaler, to create the 10-bit time base. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 16.4.1 PWM PERIOD The PWM period is specified by writing to the PR2 register ...

Page 152

... FFh FFh Preliminary ⎛ ⎝ F OSC ⎜ ⎜ log ⎝ ⎛ TMR2 Prescale Value PWM bits log(2) 156.25 kHz 312.50 kHz 416.67 kHz 3Fh 1Fh 17h 8 7 6.58 © 2007 Microchip Technology Inc. ...

Page 153

... Duty Cycle = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (ECCP1DEL<6:0>) OSC Note 1: Dead-band delay is programmed using the ECCP1DEL register (see Section 16.4.6 “Programmable Dead-Band Delay”). © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Duty Cycle Period (1) Delay Delay Duty Cycle ...

Page 154

... Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high. V+ FET Driver P1A Load FET Driver P1B V- V+ FET Driver Load FET Driver V- Preliminary HALF-BRIDGE PWM OUTPUT Period td (1) ( FET Driver FET Driver © 2007 Microchip Technology Inc. ...

Page 155

... Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active-high. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 P1A, P1B, P1C and P1D outputs are multiplexed with the PORTC<2> and PORTD<7:5> data latches. The TRISC<2> and TRISD<7:5> bits must be cleared to make the P1A, P1B, P1C and P1D pins outputs ...

Page 156

... Reduce PWM for a PWM period before changing directions. 2. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. Preliminary QC FET Driver FET Driver QD © 2007 Microchip Technology Inc. ...

Page 157

... Note 1: All signals are shown as active-high the turn-on delay of power switch QC and its driver the turn-off delay of power switch QD and its driver. OFF © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 (1) Period DC (Note 2) , depending on the Timer2 prescaler value. The modulated P1B and P1D signals ...

Page 158

... PWM period. When the ECCPASE bit is cleared, the PWM outputs will return to normal operation at the beginning of the next PWM period. Note: Writing to the ECCPASE bit is disabled while a shutdown condition is active. Preliminary driving). The ECCPASE bit © 2007 Microchip Technology Inc. ...

Page 159

... PSSBD1:PSSBD0: Pins B and D Shutdown State Control bits 1x = Pins B and D tri-state 01 = Drive Pins B and D to ‘1’ Drive Pins B and D to ‘0’ Note 1: Reserved on 28-pin devices; maintain these bits clear. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 R/W-0 R/W-0 R/W-0 (1) (1) ...

Page 160

... PWM period begins. PWM Period Normal PWM Shutdown Shutdown Event Occurs Event Clears PWM Period Normal PWM Shutdown Shutdown Event Occurs Event Clears Preliminary PWM Resumes ECCPASE Cleared by Firmware PWM Resumes © 2007 Microchip Technology Inc. ...

Page 161

... Wait until TMRn overflows (TMRnIF bit is set). • Enable the CCP1/P1A, P1B, P1C and/or P1D pin outputs by clearing the respective TRIS bits. • Clear the ECCPASE bit (ECCP1AS<7>). © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 16.4.10 OPERATION IN POWER-MANAGED MODES In Sleep mode, all clock sources are disabled. Timer2 will not increment and the state of the module will not change ...

Page 162

... Bit 2 Bit 1 Bit 0 Values on page INT0IF RBIF 49 PD POR BOR 48 TMR2IF TMR1IF 52 TMR2IE TMR1IE 52 TMR2IP TMR1IP 52 TMR3IF CCP2IF 52 TMR3IE CCP2IE 52 TMR3IP CCP2IP TMR1CS TMR1ON TMR3CS TMR3ON CCP1M1 CCP1M0 51 (2) (2) PSSBD1 PSSBD0 51 (2) (2) (2) PDC2 PDC1 PDC0 51 © 2007 Microchip Technology Inc. ...

Page 163

... MSSP 2 module is operated in SPI mode. Additional details are provided under the individual sections. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 17.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four ...

Page 164

... SSPIF interrupt is set. During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. R-0 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R-0 R bit Bit is unknown © 2007 Microchip Technology Inc. ...

Page 165

... In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 2: When enabled, these pins must be properly configured as input or output. 3: Bit combinations not specifically listed here are either reserved or implemented in I © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 R/W-0 R/W-0 R/W-0 CKP ...

Page 166

... Example 17-1 shows the loading of the SSPBUF (SSPSR) for data transmission. The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPBUF register. Additionally, the MSSP Status register (SSPSTAT) indicates the various status conditions. Preliminary © 2007 Microchip Technology Inc. ...

Page 167

... Serial Input Buffer (SSPBUF) Shift Register (SSPSR) LSb MSb PROCESSOR 1 © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 17.3.4 TYPICAL CONNECTION Figure 17-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their pro- grammed clock edge and latched on the opposite edge of the clock ...

Page 168

... SMP bit. The time when the SSPBUF is loaded with the received data is shown. bit 5 bit 4 bit 2 bit 1 bit 3 bit 5 bit 4 bit 3 bit 2 bit 1 Preliminary ) Clock Modes bit 0 bit 0 bit 0 bit 0 Next Q4 Cycle after Q2↓ © 2007 Microchip Technology Inc. ...

Page 169

... SSPIF Interrupt Flag SSPSR to SSPBUF © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 must be high. When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output ...

Page 170

... Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF DS39755B-page 168 bit 6 bit 2 bit 5 bit 4 bit 3 bit 6 bit 3 bit 2 bit 5 bit 4 Preliminary bit 1 bit 0 bit 0 Next Q4 Cycle after Q2↓ bit 1 bit 0 bit 0 Next Q4 Cycle after Q2↓ © 2007 Microchip Technology Inc. ...

Page 171

... These bits are unimplemented in 28-pin devices; always maintain these bits clear. 2: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 17.3.9 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer ...

Page 172

... SSPIF interrupt is set. Addr Match During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. Set, Reset S, P bits (SSPSTAT reg) Preliminary 2 C operation mode operation. The 2 C Slave mode. When the © 2007 Microchip Technology Inc. ...

Page 173

... This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. 3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 2 C™ MODE) ...

Page 174

... DS39755B-page 172 2 C™ MODE) R/W-0 R/W-0 R/W-0 CKP SSPM3 SSPM2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2 C conditions were not valid for a (1) /(4 * (SSPADD + 1)) OSC Preliminary R/W-0 R/W-0 SSPM1 SSPM0 bit Bit is unknown (1) © 2007 Microchip Technology Inc. ...

Page 175

... For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). 2: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 2 C™ MODE) ...

Page 176

... C module is active, these bits may not be set (no (1) R/W-0 R/W-0 ADD4 ADD3 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2 C™ Slave mode. MSSP Baud Rate register in I Preliminary R/W-0 R/W-0 R/W-0 ADD2 ADD1 ADD0 bit Bit is unknown 2 C Master mode. © 2007 Microchip Technology Inc. ...

Page 177

... The high and low times of the specification, as well as the requirement of the MSSP module, are shown in timing parameter 100 and parameter 101. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 17.4.3.1 Addressing Once the MSSP module has been enabled, it waits for a Start condition to occur. Following the Start condition, the 8 bits are shifted into the SSPSR register ...

Page 178

... Significant bits of the address. 2: The two Most Significant bits of the address are not affected by address masking. 0xA8, 0xAA, 0xAC, 0xAE 0xA4, 0xA5, 0xA6, 0xA7 0xA8, 0xA9, 0xAA 0xAB 0xAC, 0xAD, 0xAE, 0xAF Preliminary masks the two Least © 2007 Microchip Technology Inc. ...

Page 179

... The clock must be released by setting bit, CKP (SSPCON1<4>). See Section 17.4.4 “Clock Stretching” for more detail. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 17.4.3.4 Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set ...

Page 180

... PIC18F2423/2523/4423/4523 2 FIGURE 17-8: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) DS39755B-page 178 Preliminary © 2007 Microchip Technology Inc. ...

Page 181

... FIGURE 17-9: I C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01011 (RECEPTION, 7-BIT ADDRESS) © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Preliminary DS39755B-page 179 ...

Page 182

... PIC18F2423/2523/4423/4523 2 FIGURE 17-10: I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) DS39755B-page 180 Preliminary © 2007 Microchip Technology Inc. ...

Page 183

... FIGURE 17-11: I C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01001 (RECEPTION, 10-BIT ADDRESS) © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Preliminary DS39755B-page 181 ...

Page 184

... PIC18F2423/2523/4423/4523 2 FIGURE 17-12: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) DS39755B-page 182 Preliminary © 2007 Microchip Technology Inc. ...

Page 185

... FIGURE 17-13: I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Preliminary DS39755B-page 183 ...

Page 186

... R/W bit set to ‘1’. After the third address sequence is performed, the UA bit is not set, the module is now configured in Transmit mode and clock stretching is controlled by the BF flag as in 7-Bit Slave Transmit mode (see Figure 17-13). Preliminary © 2007 Microchip Technology Inc. ...

Page 187

... SDA DX SCL CKP WR SSPCONx © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other 2 devices on the I C bus have deasserted SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 17-14) ...

Page 188

... PIC18F2423/2523/4423/4523 2 FIGURE 17-15: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) DS39755B-page 186 Preliminary © 2007 Microchip Technology Inc. ...

Page 189

... FIGURE 17-16: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS) © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Preliminary DS39755B-page 187 ...

Page 190

... UA bit will not be set and the slave will begin receiving data after the Acknowledge (Figure 17-17). Address is compared to General Call Address after ACK, set interrupt R ACK Cleared in software SSPBUF is read Preliminary Receiving Data ACK ‘0’ ‘1’ © 2007 Microchip Technology Inc. ...

Page 191

... Generate a Stop condition on SDA and SCL. FIGURE 17-18: MSSP BLOCK DIAGRAM (I SDA SDA In SCL SCL In Bus Collision © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Note: The MSSP module, when configured Master mode, does not allow queueing of events. For instance, the user is not ...

Page 192

... SSPCON2 register (SSPCON2<6>). 10. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. 11. The user generates a Stop condition by setting the Stop Enable bit, PEN (SSPCON2<2>). 12. Interrupt is generated once the Stop condition is complete. Preliminary © 2007 Microchip Technology Inc. ...

Page 193

... The I C interface does not conform to the 400 kHz I 100 kHz) in all details, but may be used with care where higher rates are required by the application. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Once the given operation is complete (i.e., transmis- sion of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin will remain in its last state ...

Page 194

... DX – 1 SCL allowed to transition high BRG decrements on Q2 and Q4 cycles 02h 01h 00h (hold off) SCL is sampled high, reload takes place and BRG starts its count Preliminary 03h 02h © 2007 Microchip Technology Inc. ...

Page 195

... FIGURE 17-21: FIRST START BIT TIMING Write to SEN bit occurs here SDA SCL © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Note the beginning of the Start condition, the SDA and SCL pins are already sam- pled low during the Start condition, the ...

Page 196

... SSPCON2 is disabled until the Repeated Start condition is complete. S bit set by hardware SDA = 1, At completion of Start bit, SCL = 1 hardware clears RSEN bit and sets SSPIF BRG BRG BRG Write to SSPBUF occurs here T BRG Sr = Repeated Start Preliminary 1st bit T BRG © 2007 Microchip Technology Inc. ...

Page 197

... SSPSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). WCOL must be cleared in software. © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 17.4.10.3 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is ...

Page 198

... PIC18F2423/2523/4423/4523 2 FIGURE 17-23: I C™ MASTER MODE WAVEFORM (TRANSMISSION 10-BIT ADDRESS) DS39755B-page 196 Preliminary © 2007 Microchip Technology Inc. ...

Page 199

... FIGURE 17-24: I C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) © 2007 Microchip Technology Inc. PIC18F2423/2523/4423/4523 Preliminary DS39755B-page 197 ...

Page 200

... PEN bit (SSPCON2<2>) is cleared by hardware and the SSPIF bit is set T BRG BRG BRG BRG SCL brought high after T BRG SDA asserted low before rising edge of clock to setup Stop condition Preliminary WCOL Status Flag ACKEN automatically cleared Cleared in software BRG © 2007 Microchip Technology Inc. ...

Related keywords