DS5002FPM-16+ Maxim Integrated Products, DS5002FPM-16+ Datasheet - Page 11

• Manufacturer Part Number: DS5002FPM-16+
• Description: IC MPU SECURE 16MHZ 80-TQFP
• Manufacturer: Maxim Integrated Products
• Series: DS500xr

Specifications of DS5002FPM-16+

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SIO, UART/USART
• Peripherals: Power-Fail Reset, WDT
• Number Of I /o: 32
• Program Memory Type: SRAM
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-MQFP, 80-PQFP
• Processor Series: DS500x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Operating Supply Voltage: 3.85 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• Program Memory Size: 32 KB, 64 KB, 128 KB
• Interface Type: UART
• Package: 80MQFP
• Device Core: 8051
• Family Name: DS500x
• Maximum Speed: 16 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIN DESCRIPTION
80, 76, 4, 6,
11, 9, 7, 5,
15, 17, 19,
21, 25, 27,
49, 50, 51,
56, 58, 60,
20, 24, 26,
28, 30, 33,
71, 69, 67,
65, 61, 59,
1, 79, 77,
16, 8, 18,
29, 31
64, 66
47, 48
35, 37
57, 55
PIN
75
36
38
39
40
41
44
45
46
34
70
52
13
12
54
10
74
63
2
XTAL2, XTAL1
BA14–BA0
P0.0–P0.7
P1.0–P1.7
P2.0–P2.7
P3.2/INT0
P3.3/INT1
P3.0/RXD
BD7–BD0
P3.1/TXD
P3.6/WR
P3.7/RD
P3.4/T0
P3.5/T1
NAME
GND
V
RST
ALE
R/W
CE1
CE2
CE3
V
V
CCO
CC
LI
General-Purpose I/O Port 0. This port is open-drain and cannot drive a logic 1. It requires
external pullups. Port 0 is also the multiplexed expanded address/data bus. When used in
this mode, it does not require pullups.
General-Purpose I/O Port 1
General-Purpose I/O Port 2. Also serves as the MSB of the expanded address bus.
General-Purpose I/O Port Pin 3.0. Also serves as the receive signal for the on-board UART.
This pin should not be connected directly to a PC COM port.
General-Purpose I/O Port Pin 3.1. Also serves as the transmit signal for the on-board
UART. This pin should not be connected directly to a PC COM port.
General-Purpose I/O Port Pin 3.2. Also serves as the active-low external interrupt 0.
General-Purpose I/O Port Pin 3.3. Also serves as the active-low external interrupt 1.
General-Purpose I/O Port Pin 3.4. Also serves as the timer 0 input.
General-Purpose I/O Port Pin 3.5. Also serves as the timer 1 input.
General-Purpose I/O Port Pin. Also serves as the write strobe for Expanded bus operation.
General-Purpose I/O Port Pin. Also serves as the read strobe for Expanded bus operation.
Active-High Reset Input. A logic 1 applied to this pin activates a reset state. This pin is
pulled down internally so this pin can be left unconnected if not used. An RC power-on reset
circuit is not needed and is not recommended.
Address Latch Enable. Used to demultiplex the multiplexed expanded address/data bus on
port 0. This pin is normally connected to the clock input on a ’373 type transparent latch.
Crystal Connections. Used to connect an external crystal to the internal oscillator. XTAL1 is
the input to an inverting amplifier and XTAL2 is the output.
Logic Ground
Power Supply, +5V
V
V
remains isolated from a load. When V
V
Lithium Voltage Input. Connect to a lithium cell greater than V
V
Byte-Wide Address Bus Bits 14–0. This bus is combined with the nonmultiplexed data bus
(BD7–BD0) to access NV SRAM. Decoding is performed using CE1 to CE4. Therefore, BA15
is not actually needed. Read/write access is controlled by R/W. BA14–0 connect directly to an
8k, 32k, or 128k SRAM. If an 8k RAM is used, BA13 and BA14 are unconnected. If a 128k
SRAM is used, the micro converts CE2 and CE3 to serve as A16 and A15, respectively.
Byte-Wide Data Bus Bits 7–0. This 8-bit bidirectional bus is combined with the
nonmultiplexed address bus (BA14–BA0) to access NV SRAM. Decoding is performed on
CE1 and CE2. Read/write access is controlled by R/W. D7–D0 connect directly to an SRAM,
and optionally to a real-time clock or other peripheral.
Read/Write (Active Low). This signal provides the write enable to the SRAMs on the byte-
wide bus. It is controlled by the memory map and partition. The blocks selected as program
(ROM) are write-protected.
Active-Low Chip Enable 1. This is the primary decoded chip enable for memory access on
the byte-wide bus. It connects to the chip-enable input of one SRAM. CE1 is lithium-backed.
It remains in a logic-high inactive state when V
Active-Low Chip Enable 2. This chip enable is provided to access a second 32k block of
memory. It connects to the chip-enable input of one SRAM. When MSEL = 0, the micro
converts CE2 into A16 for a 128k x 8 SRAM. CE2 is lithium-backed and remains at a logic
high when V
Active-Low Chip Enable 3. This chip enable is provided to access a third 32k block of
memory. It connects to the chip enable input of one SRAM. When MSEL = 0, the micro
converts CE3 into A15 for a 128k x 8 SRAM. CE3 is lithium-backed and remains at a logic
high when V
CC
CC
CCO
LIMAX
. When power is above the lithium input, power is drawn from V
Output. This is switched between V
should be connected to the V
as shown in the electrical specifications. Nominal value is +3V.
CC
CC
falls below V
falls below V
11 of 25
LI
LI
.
.
CC
pin of an SRAM.
CC
CC
is below V
FUNCTION
and V
CC
LI
falls below V
by internal circuits based on the level of
LI
, the V
CCO
LI
switches to the V
.
LIMIN
CC
and no greater than
. The lithium cell
LI
source.