C8051F121-GQ Silicon Laboratories Inc, C8051F121-GQ Datasheet - Page 294

• Manufacturer Part Number: C8051F121-GQ
• Description: IC 8051 MCU FLASH 128K 64TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F12xr

Specifications of C8051F121-GQ

• Program Memory Type: FLASH
• Program Memory Size: 128KB (128K x 8)
• Package / Case: 64-TQFP, 64-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 32
• Ram Size: 8.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x8b, 8x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F1x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8.25 KB
• Interface Type: I2C/SMBus/SPI/UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F120DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 8-bit or 8-ch x 12-bit
• On-chip Dac: 2-ch x 12-bit
• No. Of I/o's: 32
• Ram Memory Size: 8448Byte
• Cpu Speed: 100MHz
• No. Of Timers: 5
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1224 - DEVKIT-F120/21/22/23/24/25/26/27
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1225

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
21.3. Frame and Transmission Error Detection
All Modes:
The Transmit Collision bit (TXCOL0 bit in register SSTA0) reads ‘1’ if user software writes data to the
SBUF0 register while a transmit is in progress.
Modes 1, 2, and 3:
The Receive Overrun bit (RXOV0 in register SSTA0) reads ‘1’ if a new data byte is latched into the receive
buffer before software has read the previous byte. The Frame Error bit (FE0 in register SSTA0) reads ‘1’ if
an invalid (low) STOP bit is detected.
294
RX
Master
Device
Figure 21.7. UART Multi-Processor Mode Interconnect Diagram
TX
RX
Device
Slave
TX
Rev. 1.4
RX
Device
Slave
TX
RX
Device
Slave
TX
+5V