C8051F561-IQ Silicon Laboratories Inc, C8051F561-IQ Datasheet - Page 47

• Manufacturer Part Number: C8051F561-IQ
• Description: IC 8051 MCU 32K FLASH 32-QFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F56xr

Specifications of C8051F561-IQ

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 32-QFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), CAN, SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.25 V
• Data Converters: A/D 25x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: C8051F5x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 2304 B
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 25
• Operating Supply Voltage: 1.8 V to 5.25 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F560DK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1691 - KIT DEVELOPMENT FOR C8051F560
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1696

6. 12-Bit ADC (ADC0)
The ADC0 on the C8051F55x/56x/57x consists of an analog multiplexer (AMUX0) with 33, 25, or 18 total
input selections and a 200 ksps, 12-bit successive-approximation-register (SAR) ADC with integrated
track-and-hold, programmable window detector, programmable attenuation (1:2), and hardware accumula-
tor. The ADC0 subsystem has a special Burst Mode which can automatically enable ADC0, capture and
accumulate samples, then place ADC0 in a low power shutdown mode without CPU intervention. The
AMUX0, data conversion modes, and window detector are all configurable under software control via the
Special Function Registers shows in Figure 6.1. ADC0 inputs are single-ended and may be configured to
measure P0.0-P3.7, the Temperature Sensor output, V
ence for ADC0 is selected as described in Section “6.6. Temperature Sensor” on page 67. ADC0 is
enabled when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1, or when performing
conversions in Burst Mode. ADC0 is in low power shutdown when AD0EN is logic 0 and no Burst Mode
conversions are taking place.
P3.1-P3.7 available on 40-
P2.2-P2.7, P3.0 available
on 40-pin and 32-pin
pin packages
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
P3.7
packages
Temp Sensor
GND
VDD
AMUX0
35-to-1
Figure 6.1. ADC0 Functional Block Diagram
ADC0GNH
ADC0MX
25 MHz Max
Burst Mode
Oscillator
Selectable
Gain
Conversion
ADC0GNL
SYSCLK
Start
ADC0GNA
Rev. 1.1
Burst Mode
ADC0TK
Logic
ADC0CF
DD
, or GND with respect to GND. The voltage refer-
ADC
12-Bit
SAR
C8051F55x/56x/57x
ADC0GTH ADC0GTL
ADC0LTH
VDD
ADC0CN
ADC0LTL
Conversion
Start
00
01
10
11
32
Accumulator
AD0WINT
Compare
AD0BUSY (W)
Timer 1 Overflow
CNVSTR Input
Timer 2 Overflow
Window
Logic
47