C8051F226-GQ Silicon Laboratories Inc, C8051F226-GQ Datasheet
C8051F226-GQ
Manufacturer Part Number
C8051F226-GQ
Description
IC 8051 MCU 8K FLASH 48TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F2xxr
Specifications of C8051F226-GQ
Program Memory Type
FLASH
Program Memory Size
8KB (8K x 8)
Package / Case
48-TQFP, 48-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
32
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 32x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F2x
Core
8051
Data Bus Width
8 bit
Data Ram Size
1.25 KB
Interface Type
SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F226DK
Minimum Operating Temperature
- 40 C
On-chip Adc
32-ch x 8-bit
Package
48TQFP
Device Core
8051
Family Name
C8051F2xx
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1241 - DEV KIT F220/221/226/230/231/236
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1240
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F226-GQ
Manufacturer:
SILICON
Quantity:
10
Company:
Part Number:
C8051F226-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F226-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Analog Peripherals
8-Bit ADC
-
-
-
-
-
-
Two comparators
-
-
V
On-Chip JTAG Debug
-
-
-
-
General Purpose
DD
MONEN
XTAL1
XTAL2
±1/2 LSB INL; no missing codes
Programmable throughput up to 100 ksps
32 external inputs (each port I/O can be configured as an ADC input on-
the-fly)
Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5
Data-dependent windowed interrupt generator
V
Programmable hysteresis
Configurable to generate interrupts or reset
On-chip emulation circuitry facilitates full-speed, non-intrusive, in-circuit
emulation
Supports breakpoints, single stepping, watchpoints, inspect/modify
memory, and registers
Superior performance to emulation systems using ICE-chips, target
pods, and sockets
Fully compliant with IEEE 1149.1 specification
GND
GND
VDD
VDD
TMS
TDO
TCK
RST
REF
Monitor and Brown-out Detector
TDI
NC
NC
NC
from external pin or V
Analog/Digital
Power
Oscillator
Oscillator
External
Monitor
Internal
Circuit
JTAG
Logic
VDD
DD
Debug HW
WDT
System Clock
25 MIPS, 8 kB Flash, 8-Bit ADC, 48-Pin Mixed-Signal MCU
Reset
Copyright © 2004 by Silicon Laboratories
C
o
8
0
5
1
e
r
SFR Bus
8 kB FLASH
1024 byte
256 byte
XRAM
RAM
High-Speed 8051 µC Core
-
-
-
Memory
-
-
Digital Peripherals
-
-
-
-
Clock Sources
-
-
-
Supply Voltage: 2.7 to 3.6 V
-
-
48-Pin TQFP
-
Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
Up to 25 MIPS throughput with 25 MHz system clock
Expanded interrupt handler; up to 21 interrupt sources
1280 bytes data RAM
8 kB Flash; in-system programmable in 512 byte sectors (512 bytes are
reserved)
32 port I/O; all are 5 V tolerant
Hardware SPI™ and UART serial ports available concurrently
3 general-purpose 16-bit counter/timers
Dedicated watchdog timer; bidirectional reset
Internal programmable oscillator: 2–16 MHz
External oscillator: Crystal, RC, C, or Clock
Can switch between clock sources on-the-fly
Typical operating current: 9 mA at 25 MHz
Typical stop mode current: <0.1 uA
Temperature Range: –40 to +85 °C
CP0
CP1
Timer 0
Timer 1
Timer 2
Port 0
UART
Port 1
Port 2
Port 3
Latch
Latch
Latch
Latch
SPI
CP0
CP1
VDD
100 ksps
8-bit
ADC
CP0+
CP0-
CP1+
CP1-
SYSCLK
M
M
M
P
U
X
P
U
X
P
U
X
0
1
2
PGA
C8051F226
M
U
A
X
AIN0-AIN31
P
D
P
D
P
D
P
D
0
v
1
v
2
v
3
v
r
r
r
r
VREF
P0.0/TX
P0.1/RX
P0.2//INT0
P0.3//INT1
P0.4/T0
P0.5/T1
P0.6/T2
P0.7/T2EX
P1.0/CP0+
P1.1/CP0-
P1.2/CP0
P1.3/CP1+
P1.4/CP1-
P1.5/CP1
P1.6/SYSCLK
P1.7
P2.0/NSS
P2.1/MISO
P2.2/MOSI
P2.3/SCK
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
6.15.2004
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C8051F226-GQ Summary of contents
Page 1
... Timer 1 Timer 2 Port 1 Latch FLASH 0 CP0 256 byte 5 RAM 1 CP1 1024 byte XRAM C Port 2 o SFR Bus Latch r SPI e Port 3 Latch Copyright © 2004 by Silicon Laboratories C8051F226 P0.0/TX P P0.1/ P0.2//INT0 0 P0.3//INT1 D P0.4/T0 P0.5/ P0.6/ P0.7/T2EX X P1.0/CP0+ P P1.1/CP0 P1.2/CP0 1 CP0+ P1 ...
Page 2
... Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders CONDITIONS MIN 2.7 Monitor Disabled DD Monitor DD Monitor –3 mA, Port I/O push-pull V – 0 8 –0.25 –5 –10 C8051F226DK Development Kit MIN NOM MAX (mm) (mm) (mm 1.20 A1 0.05 - 0.15 A2 0.95 1.00 1.05 b 0.17 0.22 ...