C8051T610-GQ Silicon Laboratories Inc, C8051T610-GQ Datasheet
C8051T610-GQ
Specifications of C8051T610-GQ
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C8051T610-GQ Summary of contents
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... Clock Sources - Internal oscillator: 24.5 MHz with ±2% accuracy supports crystal-less UART operation - External oscillator: RC CMOS Clock - Can switch between clock sources on-the-fly; useful in power saving modes Packages - 32-pin LQFP (C8051T610/2/4) - 28-pin QFN (C8051T611/3/5) - 24-pin QFN (C8051T616/7) ANALOG PERIPHERALS UART SMBus 10-bit + ...
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... C8051T610/1/2/3/4/5/6/7 2 Rev 1.0 ...
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... Tracking Modes......................................................................................... 41 8.3.3. Settling Time Requirements...................................................................... 42 8.4. Programmable Window Detector....................................................................... 46 8.4.1. Window Detector Example........................................................................ 48 8.5. ADC0 Analog Multiplexer (C8051T610/1/2/3/6 only)......................................... 49 9. Temperature Sensor (C8051T610/1/2/3/6 only) ..................................................... 51 9.1. Calibration ......................................................................................................... 51 10. Voltage Reference Options ................................................................................... 54 11. Voltage Regulator (REG0) ..................................................................................... 56 12. Comparator0 and Comparator1............................................................................ 58 12.1. Comparator Multiplexers ................................................................................. 65 13 ...
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... C8051T610/1/2/3/4/5/6/7 16.2. Interrupt Register Descriptions ........................................................................ 87 16.3. External Interrupts INT0 and INT1................................................................... 92 17. EPROM Memory ..................................................................................................... 94 17.1. Programming and Reading the EPROM Memory ........................................... 94 17.1.1. EPROM Write Procedure ........................................................................ 94 17.1.2. EPROM Read Procedure........................................................................ 95 17.2. Security Options .............................................................................................. 95 17.3. Program Memory CRC .................................................................................... 96 17.3.1. Performing 32-bit CRCs on Full EPROM Content .................................. 96 17 ...
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... Timer 2 .......................................................................................................... 180 25.2.1. 16-bit Timer with Auto-Reload............................................................... 180 25.2.2. 8-bit Timers with Auto-Reload............................................................... 181 25.3. Timer 3 .......................................................................................................... 185 25.3.1. 16-bit Timer with Auto-Reload............................................................... 185 25.3.2. 8-bit Timers with Auto-Reload............................................................... 186 26. Programmable Counter Array............................................................................. 190 26.1. PCA Counter/Timer ....................................................................................... 191 C8051T610/1/2/3/4/5/6/7 Rev 1.0 5 ...
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... C8051T610/1/2/3/4/5/6/7 26.2. PCA0 Interrupt Sources................................................................................. 192 26.3. Capture/Compare Modules ........................................................................... 193 26.3.1. Edge-triggered Capture Mode............................................................... 194 26.3.2. Software Timer (Compare) Mode.......................................................... 195 26.3.3. High-Speed Output Mode ..................................................................... 196 26.3.4. Frequency Output Mode ....................................................................... 197 26.3.5. 8-bit Pulse Width Modulator Mode ....................................................... 198 26.3.6. 16-Bit Pulse Width Modulator Mode..................................................... 199 26 ...
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... List of Figures 1. System Overview Figure 1.1. C8051T610/2/4 Block Diagram (32-pin LQFP) ..................................... 16 Figure 1.2. C8051T611/3/5 Block Diagram (28-pin QFN) ....................................... 17 Figure 1.3. C8051T616/7 Block Diagram (24-pin QFN) .......................................... 18 3. Pin Definitions Figure 3.1. LQFP-32 Pinout Diagram (Top View) .................................................... 22 Figure 3.2. QFN-28 Pinout Diagram (Top View) ..................................................... 23 Figure 3 ...
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... C8051T610/1/2/3/4/5/6/7 19. Reset Sources Figure 19.1. Reset Sources ................................................................................... 100 Figure 19.2. Power-On and VDD Monitor Reset Timing ....................................... 101 20. Oscillators and Clock Selection Figure 20.1. Oscillator Options .............................................................................. 106 21. Port Input/Output Figure 21.1. Port I/O Functional Block Diagram .................................................... 113 Figure 21.2. Port I/O Cell Block Diagram .............................................................. 115 Figure 21 ...
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... Figure 26.7. PCA Frequency Output Mode ........................................................... 197 Figure 26.8. PCA 8-Bit PWM Mode Diagram ........................................................ 198 Figure 26.9. PCA 16-Bit PWM Mode ..................................................................... 199 Figure 26.10. PCA Module 4 with Watchdog Timer Enabled ................................ 200 27. C2 Interface Figure 27.1. Typical C2 Pin Sharing ...................................................................... 215 C8051T610/1/2/3/4/5/6/7 Rev 1.0 9 ...
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... C8051T610/1/2/3/4/5/6/7 List of Tables 2. Ordering Information Table 2.1. Product Selection Guide ......................................................................... 19 3. Pin Definitions Table 3.1. Pin Definitions for the C8051T610/1/2/3/4/5/6/7 ..................................... 20 4. LQFP-32 Package Specifications Table 4.1. LQFP-32 Package Dimensions .............................................................. 25 Table 4.2. LQFP-32 PCB Land Pattern Dimesions ................................................. 26 5. QFN-28 Package Specifications Table 5.1. QFN-28 Package Dimensions ................................................................ 27 Table 5 ...
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... Enhanced Serial Peripheral Interface (SPI0) Table 24.1. SPI Slave Timing Parameters ............................................................ 169 26. Programmable Counter Array Table 26.1. PCA Timebase Input Options ............................................................. 191 Table 26.2. PCA0CPM Bit Settings for PCA Capture/Compare Modules ............. 193 Table 26.3. Watchdog Timer Timeout Intervals1 ................................................... 202 27. C2 Interface C8051T610/1/2/3/4/5/6/7 Rev 1.0 11 ...
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... C8051T610/1/2/3/4/5/6/7 List of Registers SFR Definition 8.1. ADC0CF: ADC0 Configuration ...................................................... 43 SFR Definition 8.2. ADC0H: ADC0 Data Word MSB .................................................... 44 SFR Definition 8.3. ADC0L: ADC0 Data Word LSB ...................................................... 44 SFR Definition 8.4. ADC0CN: ADC0 Control ................................................................ 45 SFR Definition 8.5. ADC0GTH: ADC0 Greater-Than Data High Byte .......................... 46 SFR Definition 8.6. ADC0GTL: ADC0 Greater-Than Data Low Byte ............................ 46 SFR Definition 8 ...
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... SFR Definition 26.4. PCA0L: PCA Counter/Timer Low Byte ...................................... 206 SFR Definition 26.5. PCA0H: PCA Counter/Timer High Byte ..................................... 206 SFR Definition 26.6. PCA0CPLn: PCA Capture Module Low Byte ............................. 207 SFR Definition 26.7. PCA0CPHn: PCA Capture Module High Byte ........................... 207 C8051T610/1/2/3/4/5/6/7 Rev 1.0 13 ...
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... C8051T610/1/2/3/4/5/6/7 C2 Register Definition 27.1. C2ADD: C2 Address ...................................................... 208 C2 Register Definition 27.2. DEVICEID: C2 Device ID ............................................... 209 C2 Register Definition 27.3. REVID: C2 Revision ID .................................................. 209 C2 Register Definition 27.4. DEVCTL: C2 Device Control .......................................... 210 C2 Register Definition 27.5. EPCTL: EPROM Programming Control Register ........... 210 C2 Register Definition 27.6. EPDAT: C2 EPROM Data .............................................. 211 C2 Register Definition 27 ...
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... C8051T610/1/2/3/4/5/6/7 devices are truly stand-alone, system-on-a-chip solutions. User software has complete control of all peripherals and may individually shut down any or all peripherals for power savings. Code written for the C8051T610/1/2/3/4/5/6/7 family of processors will run on the C8051F310 Mixed-Sig- nal ISP Flash microcontroller, providing a quick, cost-effective way to develop code without requiring spe- cial emulator circuitry. The C8051T610/1/2/3/4/5/6/7 processors include Silicon Laboratories’ ...
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... SRAM C2D 1 k Byte XRAM Peripheral Power VDD Regulator Core Power GND EXTCLK External Clock Circuit System Clock Configuration Figure 1.1. C8051T610/2/4 Block Diagram (32-pin LQFP) 16 Port I/O Configuration Digital Peripherals UART Timers Priority Crossbar PCA/ Decoder WDT SMBus SPI ...
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... Byte XRAM Peripheral Power SYSCLK VDD Regulator Core Power GND EXTCLK External Clock Circuit System Clock Configuration Figure 1.2. C8051T611/3/5 Block Diagram (28-pin QFN) C8051T610/1/2/3/4/5/6/7 Port I/O Configuration Digital Peripherals UART Timers Priority Crossbar PCA/ Decoder WDT SMBus SPI Crossbar Control ...
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... C8051T610/1/2/3/4/5/6/7 Power On CIP-51 8051 Reset Controller Core Reset 16 k Byte EPROM Program Memory Debug / C2CK/RST Programming Hardware 256 byte SRAM C2D 1 k Byte XRAM Peripheral Power VDD Regulator Core Power GND EXTCLK External Clock Circuit System Clock Configuration Figure 1.3. C8051T616/7 Block Diagram (24-pin QFN) ...
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... Ordering Information Table 2.1. Product Selection Guide C8051T610-GQ 25 16k* 1280 C8051T611-GM 25 16k* 1280 C8051T612- 1280 C8051T613- 1280 C8051T614- 1280 C8051T615- 1280 C8051T616-GM 25 16k* 1280 C8051T617-GM 25 16k* 1280 * 512 Bytes Reserved for Factory Use C8051T610/1/2/3/4/5/6 — — — Rev 1 LQFP- QFN- LQFP-32 ...
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... C8051T610/1/2/3/4/5/6/7 3. Pin Definitions Table 3.1. Pin Definitions for the C8051T610/1/2/3/4/5/6/7 Pin Pin Name T610/2/4 T611/3/5 T616 GND 3 3 RST C2CK P3. C2D P0 P0 P0. VPP Pin Type Description 4 Power Supply Voltage. 3 Ground I/O Device Reset. Open-drain output of internal POR. ...
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... Table 3.1. Pin Definitions for the C8051T610/1/2/3/4/5/6/7 (Continued) Pin Pin Pin Name T610/2/4 T611/3/5 T616 P3.1 7 — P3.2 8 — P3.3 9 — P3.4 10 — C8051T610/1/2/3/4/5/6/7 Type Description 15 D I/O or Port 1. I/O or Port 1. I/O or Port 1. — D I/O or Port 1 ...
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... C8051T610/1/2/3/4/5/6/7 P0 P0.0 3 GND 4 VDD 5 RST/C2CK 6 P3.0/C2D P3 P3.2 Figure 3.1. LQFP-32 Pinout Diagram (Top View) 22 C8051T610/2/4 Top View Rev 1.0 24 P1.2 23 P1.3 22 P1.4 21 P1.5 20 P1.6 19 P1.7 18 P2.0 17 P2.1 ...
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... P0.1 1 P0.0 2 GND 3 C8051T611/3/5 VDD 4 RST/C2CK 5 P3.0/C2D 6 P2.7 7 Figure 3.2. QFN-28 Pinout Diagram (Top View) C8051T610/1/2/3/4/5/6/7 Top View GND (optional) Rev 1.0 21 P1.1 20 P1.2 19 P1.3 18 P1.4 17 P1.5 16 P1.6 15 P1.7 23 ...
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... C8051T610/1/2/3/4/5/6/7 P0.1 1 P0.0 2 GND 3 VDD 4 RST/C2CK 5 P3.0 / C2D 6 Figure 3.3. QFN-24 Pinout Diagram (Top View) 24 C8051T616/7 Top View GND (optional) Rev 1.0 18 P1.0 17 P1.1 16 P1.2 15 P1.3 14 P1.4 13 P1.5 ...
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... Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MS-026, variation BBA. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. C8051T610/1/2/3/4/5/6/7 Max Dimension Min 1. ...
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... C8051T610/1/2/3/4/5/6/7 Figure 4.2. LQFP-32 Recommended PCB Land Pattern Table 4.2. LQFP-32 PCB Land Pattern Dimesions Dimension Min C1 8.40 C2 8.40 E 0.80 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on the IPC-7351 guidelines. Solder Mask Design 3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad 60 ...
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... This drawing conforms to the JEDEC Solid State Outline MO-220, variation VHHD except for custom features D2, E2 and L which are toleranced per supplier designation. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. C8051T610/1/2/3/4/5/6/7 Max Dimension Min 1. ...
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... C8051T610/1/2/3/4/5/6/7 Figure 5.2. QFN-28 Recommended PCB Land Pattern Table 5.2. QFN-28 PCB Land Pattern Dimesions Dimension Min C1 4.80 C2 4.80 E 0.50 X1 0.20 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on the IPC-7351 guidelines. ...
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... Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC Solid State Outline MO-220, variation WGGD except for custom features D2, E2 and L which are toleranced per supplier designation. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. C8051T610/1/2/3/4/5/6/7 Max Dimension Min 0. ...
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... C8051T610/1/2/3/4/5/6/7 Figure 6.2. QFN-24 Recommended PCB Land Pattern Table 6.2. QFN-24 PCB Land Pattern Dimesions Dimension Min C1 3.90 C2 3.90 E 0.50 BSC X1 0.20 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on the IPC-7351 guidelines. Solder Mask Design 3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad 60 ...
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... Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. C8051T610/1/2/3/4/5/6/7 Conditions Min –55 – ...
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... C8051T610/1/2/3/4/5/6/7 7.2. Electrical Characteristics Table 7.2. Global Electrical Characteristics –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameter Supply Voltage (Note 1) Regulator in Normal Mode Regulator in Bypass Mode Digital Supply Current with V DD CPU Active Digital Supply Current with V DD CPU Inactive (not accessing ...
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... Port I/O push-pull –10 mA, Port I/O push-pull OH Output Low Voltage µ Input High Voltage Input Low Voltage Input Leakage Weak Pullup Off Current Weak Pullup On, V C8051T610/1/2/3/4/5/6/7 Conditions Min 0.1 DD — — — — 0 — — IN Rev 1.0 ...
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... Table 7.5. Internal Voltage Regulator Electrical Characteristics –40 to +85 °C unless otherwise specified. Parameter Input Voltage Range Bias Current Normal Mode Table 7.6. EPROM Electrical Characteristics Parameter EPROM Size C8051T610/1/6/7 EPROM Size C8051T612/3/4/5 Write Cycle Time (per Byte) Date Code 0935 and Later 2 Programming Voltage ( ...
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... ADC Input Voltage Range Sampling Capacitance 1x Gain 0.5x Gain Input Multiplexer Impedance Power Specifications Power Supply Current Operating Mode, 200 ksps (V supplied to ADC0) DD Power Supply Rejection C8051T610/1/2/3/4/5/6/7 Conditions Min 24 = 3.0 V, — DD — — – +85 °C unless otherwise specified. Conditions Min — ...
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... C8051T610/1/2/3/4/5/6/7 Table 7.9. Temperature Sensor Electrical Characteristics V – +85 °C unless otherwise specified. DD Parameter Linearity Slope Slope Error* Offset Offset Error* Note: Represents one standard deviation from the mean. Table 7.10. Voltage Reference Electrical Characteristics V = 3.0 V; –40 to +85 °C unless otherwise specified. ...
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... Inverting or Non-Inverting Input Voltage Range Input Offset Voltage Power Specifications Power Supply Rejection Powerup Time Supply Current at DC Mode 0 Mode 1 Mode 2 Mode 3 Note: Vcm is the common-mode voltage on CP0+ and CP0–. C8051T610/1/2/3/4/5/6/7 Conditions Min Typ — 240 — 240 — 400 — 400 — ...
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... C8051T610/1/2/3/4/5/6/7 7.3. Typical Performance Curves 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0 Figure 7.1. Normal Mode Digital Supply Current vs. Frequency (MPCE = 1) 2.5 2.0 1.5 1.0 0.5 0 Figure 7.2. Idle Mode Digital Supply Current vs. Frequency (MPCE = > SYSCLK (MHz) V > 1.8 V ...
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... The ADC is fully configurable under software control via Special Function Registers. The ADC may be con- figured to measure various different signals using the analog multiplexer described in Section “8.5. ADC0 Analog Multiplexer (C8051T610/1/2/3/6 only)” on page 49. The voltage reference for the ADC is selected as described in Section “10. Voltage Reference Options” on page 54. The ADC0 subsystem is enabled only when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1 ...
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... C8051T610/1/2/3/4/5/6/7 8.1. Output Code Formatting The ADC measures the input voltage with reference to GND. The registers ADC0H and ADC0L contain the high and low bytes of the output conversion code from the ADC at the completion of each conversion. Data can be right-justified or left-justified, depending on the setting of the AD0LJST bit. Conversion codes are represented as 10-bit unsigned integers ...
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... Write '1' to AD0BUSY, Timer 0, Timer 2, Timer 1 Overflow (AD0CM[2:0]=000, 001, 010, 011) SAR Clocks AD0TM=1 SAR Clocks AD0TM=0 Figure 8.2. 10-Bit ADC Track and Conversion Example Timing C8051T610/1/2/3/4/5/6/7 A. ADC Timing for External Trigger Source 15 Track Convert *Conversion Ends at rising edge 12 N/C Track Convert *Conversion Ends at rising edge ...
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... C8051T610/1/2/3/4/5/6/7 8.3.3. Settling Time Requirements A minimum tracking time is required before each conversion to ensure that an accurate conversion is per- formed. This tracking time is determined by any series impedance, including the AMUX0 resistance, the the ADC0 sampling capacitance, and the accuracy required for the conversion. Note that in delayed track- ing mode, three SAR clocks are used for tracking at the start of every conversion ...
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... Note: The AD0LJST bit is only valid for 10-bit mode (AD08BE = 0). 1 AD08BE 8-Bit Mode Enable. 0: ADC operates in 10-bit mode (normal). 1: ADC operates in 8-bit mode. Note: When AD08BE is set to 1, the AD0LJST bit is ignored. 0 AMP0GN0 ADC Gain Control Bit. 0: Gain = 0.5 1: Gain = 1 C8051T610/1/2/3/4/5/6 AD0LJST R Function – ...
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... C8051T610/1/2/3/4/5/6/7 SFR Definition 8.2. ADC0H: ADC0 Data Word MSB Bit 7 6 Name Type 0 0 Reset SFR Address = 0xBE Bit Name 7:0 ADC0H[7:0] ADC0 Data Word High-Order Bits. For AD0LJST = 0: Bits 7–2 will read 000000b. Bits 1–0 are the upper 2 bits of the 10- bit ADC0 Data Word. For AD0LJST = 1: Bits 7– ...
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... ADC0 start-of-conversion source is write AD0BUSY. 001: ADC0 start-of-conversion source is overflow of Timer 0. 010: ADC0 start-of-conversion source is overflow of Timer 2. 011: ADC0 start-of-conversion source is overflow of Timer 1. 100: ADC0 start-of-conversion source is rising edge of external CNVSTR. 101: ADC0 start-of-conversion source is overflow of Timer 3. 11x: Reserved. C8051T610/1/2/3/4/5/6 AD0BUSY AD0WINT R/W R/W ...
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... C8051T610/1/2/3/4/5/6/7 8.4. Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-pro- grammed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system response times ...
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... ADC0LTH[7:0] ADC0 Less-Than Data Word High-Order Bits. SFR Definition 8.8. ADC0LTL: ADC0 Less-Than Data Low Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0xC5 Bit Name 7:0 ADC0LTL[7:0] ADC0 Less-Than Data Word Low-Order Bits. C8051T610/1/2/3/4/5/6 ADC0LTH[7:0] R Function ADC0LTL[7:0] R/W 0 ...
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... C8051T610/1/2/3/4/5/6/7 8.4.1. Window Detector Example Figure 8.4 shows two example ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). The input voltage can range from 0 to VREF x (1023/1024) with respect to GND, and is represented by a 10-bit unsigned integer value. In the left example, an AD0WINT interrupt will be generated if the ADC0 conversion word (ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL and ADC0LTH:ADC0LTL (if 0x0040 < ...
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... ADC0 Analog Multiplexer (C8051T610/1/2/3/6 only) ADC0 on the C8051T610/1/2/3/6 uses an analog input multiplexer to select the positive input to the ADC. Any of the following may be selected as the positive input: Port 1, 2 and 3 I/O pins, the on-chip temperature sensor, or the positive power supply (V described in SFR Definition 8.9. ...
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... C8051T610/1/2/3/4/5/6/7 SFR Definition 8.9. AMX0P: AMUX0 Positive Channel Select Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0xBB Bit Name 7:5 Unused Unused. Read = 000b; Write = Don’t Care. 4:0 AMX0P[4:0] AMUX0 Positive Input Selection. Setting 00000: 00001: 00010: 00011: ...
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... Temperature Sensor (C8051T610/1/2/3/6 only) An on-chip temperature sensor is included on the C8051T610/1/2/3/6 which can be directly accessed via the ADC multiplexer. To use the ADC to measure the temperature sensor, the ADC mux channel should be configured to connect to the temperature sensor. The temperature sensor transfer function is shown in Figure 9 ...
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... C8051T610/1/2/3/4/5/6/7 5.00 4.00 3.00 2.00 1.00 0.00 -40.00 -20.00 -1.00 -2.00 -3.00 -4.00 -5.00 Figure 9.2. Temperature Sensor Error with 1-Point Calibration at 0 Celsius 52 0.00 20.00 40.00 Temperature (degrees C) Rev 1.0 5.00 4.00 3.00 2.00 1.00 0.00 60.00 80.00 -1.00 -2.00 -3 ...
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... The temperature sensor offset information is left-justified. One LSB of this measurement is equivalent to one LSB of the ADC output under the measurement conditions. 5:0 Unused Unused. Read = 000000b; Write = Don’t Care. C8051T610/1/2/3/4/5/6 TOFF[9:2] R/W Varies ...
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... C8051T610/1/2/3/4/5/6/7 10. Voltage Reference Options The Voltage reference multiplexer for the ADC is configurable to use an externally connected voltage refer- ence, the unregulated power supply voltage (V The REFSL bit in the Reference Control register (REF0CN, SFR Definition 10.1) selects the reference source for the ADC. For an external source, REFSL should be set select the VREF pin. To use V as the reference source, REFSL should be set to 1 ...
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... This bit selects the ADCs voltage reference pin used as voltage reference. REF 1: V used as voltage reference TEMPE Temperature Sensor Enable Bit. 0: Internal Temperature Sensor off. 1: Internal Temperature Sensor on. 1:0 Unused Unused. Read = 00b; Write = Don’t Care. C8051T610/1/2/3/4/5/6 REGOVR REFSL TEMPE R R/W R/W R Function Rev 1 ...
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... C8051T610/1/2/3/4/5/6/7 11. Voltage Regulator (REG0) C8051T610/1/2/3/4/5/6/7 devices include an internal voltage regulator (REG0) to regulate the internal core supply to 1.8 V from a V supply of 1.8 to 3.6 V. Two power-saving modes are built into the regulator to DD help reduce current consumption in low-power applications. These modes are accessed through the REG0CN register (SFR Definition 11 ...
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... Note external clock source is used with the Memory Power Controller enabled, and the clock frequency changes from slow (<2.0 MHz) to fast (> 2.0 MHz), the EPROM power will turn on, and clocks may be "skipped" to ensure that the EPROM power is stable before reading memory. C8051T610/1/2/3/4/5/6 ...
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... C8051T610/1/2/3/4/5/6/7 12. Comparator0 and Comparator1 C8051T610/1/2/3/4/5/6/7 devices include two on-chip programmable voltage comparators: Comparator0 is shown in Figure 12.1, Comparator1 is shown in Figure 12.2. The two comparators operate identically with the following exceptions: (1) Their input selections differ as described in Section “12.1. Comparator Multi- plexers” on page 65; (2) Comparator0 can be used as a reset source. ...
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... Section “7. Electrical Characteristics” on page 31. The Comparator response time may be configured in software via the CPTnMD registers (see SFR Defini- tion 12.2 and SFR Definition 12.4). Selecting a longer response time reduces the Comparator supply cur- rent. C8051T610/1/2/3/4/5/6/7 CPT1CN VDD + ...
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... C8051T610/1/2/3/4/5/6/7 CPn+ VIN+ + CPn CPn- _ VIN- CIRCUIT CONFIGURATION Positive Hysteresis Voltage (Programmed with CPnHYP Bits) VIN- INPUTS VIN OUTPUT V OL Positive Hysteresis Disabled Figure 12.3. Comparator Hysteresis Plot The Comparator hysteresis is software-programmable via its Comparator Control register CPTnCN (for 1). The user can program both the amount of hysteresis voltage (referred to the input voltage) and the positive and negative-going symmetry of this hysteresis around the threshold voltage. The Comparator hysteresis is programmed using Bits3– ...
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... CP0HYP[1:0] Comparator0 Positive Hysteresis Control Bits. 00: Positive Hysteresis Disabled. 01: Positive Hysteresis = 5 mV. 10: Positive Hysteresis = 10 mV. 11: Positive Hysteresis = 20 mV. 1:0 CP0HYN[1:0] Comparator0 Negative Hysteresis Control Bits. 00: Negative Hysteresis Disabled. 01: Negative Hysteresis = 5 mV. 10: Negative Hysteresis = 10 mV. 11: Negative Hysteresis = 20 mV. C8051T610/1/2/3/4/5/6 CP0FIF CP0HYP[1:0] R/W R/W R/W 0 ...
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... C8051T610/1/2/3/4/5/6/7 SFR Definition 12.2. CPT0MD: Comparator0 Mode Selection Bit 7 6 CP0RIE Name R R Type 0 0 Reset SFR Address = 0x9D Bit Name 7:6 Unused Unused. Read = 00b, Write = Don’t Care. 5 CP0RIE Comparator0 Rising-Edge Interrupt Enable. 0: Comparator0 Rising-edge interrupt disabled. 1: Comparator0 Rising-edge interrupt enabled. ...
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... CP1HYP[1:0] Comparator1 Positive Hysteresis Control Bits. 00: Positive Hysteresis Disabled. 01: Positive Hysteresis = 5 mV. 10: Positive Hysteresis = 10 mV. 11: Positive Hysteresis = 20 mV. 1:0 CP1HYN[1:0] Comparator1 Negative Hysteresis Control Bits. 00: Negative Hysteresis Disabled. 01: Negative Hysteresis = 5 mV. 10: Negative Hysteresis = 10 mV. 11: Negative Hysteresis = 20 mV. C8051T610/1/2/3/4/5/6 CP1FIF CP1HYP[1:0] R/W R/W R/W 0 ...
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... C8051T610/1/2/3/4/5/6/7 SFR Definition 12.4. CPT1MD: Comparator1 Mode Selection Bit 7 6 CP1RIE Name R R Type 0 0 Reset SFR Address = 0x9C Bit Name 7:6 Unused Unused. Read = 00b, Write = Don’t Care. 5 CP1RIE Comparator1 Rising-Edge Interrupt Enable. 0: Comparator1 Rising-edge interrupt disabled. 1: Comparator1 Rising-edge interrupt enabled. ...
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... Comparator Multiplexers C8051T610/1/2/3/4/5/6/7 devices include analog input multiplexers to connect Port I/O pins to the compar- ator inputs. The Comparator0 inputs are selected in the CPT0MX register (SFR Definition 12.5). The CMX0P1–CMX0P0 bits select the Comparator0 positive input; the CMX0N1–CMX0N0 bits select the Comparator0 negative input ...
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... C8051T610/1/2/3/4/5/6/7 SFR Definition 12.5. CPT0MX: Comparator0 MUX Selection Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0x9F Bit Name 7:6 Unused Unused, Read = 00b; Write = Don’t Care 5:4 CMX0N[1:0] Comparator0 Negative Input MUX Selection. 00: 01: 10: 11: 3:2 Unused Unused, Read = 00b; Write = Don’t Care 1:0 CMX0P[1:0] Comparator0 Positive Input MUX Selection ...
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... Unused. Read = 00b, Write = Don’t Care 5:4 CMX0N[1:0] Comparator1 Negative Input MUX Selection. 00: 01: 10: 11: 3:2 Unused Unused. Read = 00b, Write = Don’t Care 1:0 CMX0P[1:0] Comparator1 Positive Input MUX Selection. 00: 01: 10: 11: C8051T610/1/2/3/4/5/6 CMX1N[1:0] R Function P1.3 P1.7 P2.3 P2.7 P1 ...
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... C8051T610/1/2/3/4/5/6/7 13. CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft- ware. The MCU family has a superset of all the peripherals included with a standard 8051. The CIP-51 ...
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... Conditional branch instructions take one less clock cycle to complete when the branch is not taken as opposed to when the branch is taken. Table 13.1 is the CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock cycles for each instruction. C8051T610/1/2/3/4/5/6/7 2 2/3 3 ...
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... C8051T610/1/2/3/4/5/6/7 Table 13.1. CIP-51 Instruction Set Summary Mnemonic Description Arithmetic Operations ADD A, Rn Add register to A ADD A, direct Add direct byte to A ADD A, @Ri Add indirect RAM to A ADD A, #data Add immediate to A ADDC A, Rn Add register to A with carry ADDC A, direct ...
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... Exchange indirect RAM with A XCHD A, @Ri Exchange low nibble of indirect RAM with A Boolean Manipulation CLR C Clear Carry CLR bit Clear direct bit SETB C Set Carry SETB bit Set direct bit CPL C Complement Carry CPL bit Complement direct bit C8051T610/1/2/3/4/5/6/7 Bytes Rev 1.0 Clock Cycles ...
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... C8051T610/1/2/3/4/5/6/7 Table 13.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description ANL C, bit AND direct bit to Carry ANL C, /bit AND complement of direct bit to Carry ORL C, bit OR direct bit to carry ORL C, /bit OR complement of direct bit to Carry MOV C, bit Move direct bit to Carry MOV bit, C ...
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... LCALL and LJMP. The destination may be anywhere within the 8 kB program memory space. There is one unused opcode (0xA5) that performs the same function as NOP. All mnemonics copyrighted © Intel Corporation 1980. C8051T610/1/2/3/4/5/6/7 Rev 1.0 73 ...
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... C8051T610/1/2/3/4/5/6/7 13.2. CIP-51 Register Descriptions Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should always be written to the value indicated in the SFR description. Future product versions may use these bits to implement new features in which case the reset value of the bit will be the indicated value, selecting the feature's default state ...
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... Accumulator. This register is the accumulator for arithmetic operations. SFR Definition 13. Register Bit 7 6 Name Type 0 0 Reset SFR Address = 0xF0; Bit-Addressable Bit Name 7:0 B[7:0] B Register. This register serves as a second accumulator for certain arithmetic operations. C8051T610/1/2/3/4/5/6 SP[7:0] R Function ACC[7:0] R Function ...
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... C8051T610/1/2/3/4/5/6/7 SFR Definition 13.6. PSW: Program Status Word Bit Name R/W R/W Type 0 0 Reset SFR Address = 0xD0; Bit-Addressable Bit Name 7 CY Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (addition bor- row (subtraction cleared to logic 0 by all other arithmetic operations. ...
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... The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory spaces: program memory and data memory. Program and data memory share the same address space but are accessed via different instruction types. The memory organization of the C8051T610/1/2/3/4/5/6/7 device family is shown in Figure 14.1 C8051T610/1/6/7 CODE MEMORY ...
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... C8051T610/1/2/3/4/5/6/7 14.1. Program Memory The CIP-51 core has program memory space. The C8051T610/1/6/7 implements 15872 bytes of this program memory space as in-system, Byte-Programmable EPROM, organized in a contiguous block from addresses 0x0000 to 0x3FFF. Note that 512 bytes (0x3E00 – 0x3FFF) of this memory are reserved for factory use and are not available for user program storage ...
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... For example, the XRAM byte at address 0x0000 is shadowed at addresses 0x0400, 0x0800, 0x0C00, 0x1000, etc. This is a useful feature when performing a linear memory fill, as the address pointer doesn't have to be reset when reaching the RAM block boundary. C8051T610/1/2/3/4/5/6/7 Rev 1.0 79 ...
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... C8051T610/1/2/3/4/5/6/7 SFR Definition 14.1. EMI0CN: External Memory Interface Control Bit 7 6 Name R/W R/W Type 0 0 Reset SFR Address = 0xAA Bit Name 7:2 Unused Unused. Read = 000000b; Write = Don’t Care 1:0 PGSEL[1:0] XRAM Page Select. The EMI0CN register provides the high byte of the 16-bit external data memory address when using an 8-bit MOVX command, effectively selecting a 256-byte page of RAM ...
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... SFRs used to configure and access the sub-systems unique to the C8051T610/1/2/3/4/5/6/7. This allows the addition of new functionality while retaining compatibility with the MCS-51™ instruction set. Table 15.1 lists the SFRs implemented in the C8051T610/1/2/3/4/5/6/7 device family. The SFR registers are accessed anytime the direct addressing mode is used to access memory locations from 0x80 to 0xFF ...
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... C8051T610/1/2/3/4/5/6/7 Table 15.2. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address 0xE0 Accumulator ACC 0xBC ADC0 Configuration ADC0CF 0xE8 ADC0 Control ADC0CN 0xC4 ADC0 Greater-Than Compare High ADC0GTH 0xC3 ADC0 Greater-Than Compare Low ...
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... PCA0H 0xF9 PCA Counter Low PCA0L 0xD9 PCA Mode PCA0MD 0x87 Power Control PCON 0xD0 Program Status Word PSW 0xD1 Voltage Reference Control REF0CN C8051T610/1/2/3/4/5/6/7 Description Rev 1.0 Page 126 126 127 127 128 128 129 129 130 130 131 131 ...
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... C8051T610/1/2/3/4/5/6/7 Table 15.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address 0xC7 Voltage Regulator Control REG0CN 0xEF Reset Source Configuration/Status RSTSRC 0x99 UART0 Data Buffer SBUF0 0x98 UART0 Control SCON0 0xC1 SMBus Configuration ...
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... Interrupts The C8051T610/1/2/3/4/5/6/7 includes an extended interrupt system supporting a total of 14 interrupt sources with two priority levels. The allocation of interrupt sources between on-chip peripherals and exter- nal input pins varies according to the specific version of the device. Each interrupt source has one or more associated interrupt-pending flag(s) located in an SFR ...
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... C8051T610/1/2/3/4/5/6/7 16.1. MCU Interrupt Sources and Vectors The C8051T610/1/2/3/4/5/6/7 MCUs support 14 interrupt sources. Software can simulate an interrupt by setting any interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be generated and the CPU will vector to the ISR address associated with the interrupt-pending flag. MCU interrupt sources, associated vector addresses, priority order and control bits are summarized in Table 16 ...
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... The SFRs used to enable the interrupt sources and set their priority level are described in this section. Refer to the data sheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). C8051T610/1/2/3/4/5/6/7 Priority Pending Flag ...
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... C8051T610/1/2/3/4/5/6/7 SFR Definition 16.1. IE: Interrupt Enable Bit ESPI0 Name R/W R/W Type 0 0 Reset SFR Address = 0xA8; Bit-Addressable Bit Name 7 EA Enable All Interrupts. Globally enables/disables all interrupts. It overrides individual interrupt mask settings. 0: Disable all interrupt sources. 1: Enable each interrupt according to its individual mask setting. ...
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... Timer 0 interrupt set to low priority level. 1: Timer 0 interrupt set to high priority level. 0 PX0 External Interrupt 0 Priority Control. This bit sets the priority of the External Interrupt 0 interrupt. 0: External Interrupt 0 set to low priority level. 1: External Interrupt 0 set to high priority level. C8051T610/1/2/3/4/5/6 PT2 PS0 PT1 R/W ...
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... C8051T610/1/2/3/4/5/6/7 SFR Definition 16.3. EIE1: Extended Interrupt Enable 1 Bit 7 6 ET3 ECP1 Name R/W R/W Type 0 0 Reset SFR Address = 0xE6 Bit Name 7 ET3 Enable Timer 3 Interrupt. This bit sets the masking of the Timer 3 interrupt. 0: Disable Timer 3 interrupts. 1: Enable interrupt requests generated by the TF3L or TF3H flags. ...
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... ADC0 Window interrupt set to high priority level. 1 Reserved Reserved. Must Write 0. 0 PSMB0 SMBus (SMB0) Interrupt Priority Control. This bit sets the priority of the SMB0 interrupt. 0: SMB0 interrupt set to low priority level. 1: SMB0 interrupt set to high priority level. C8051T610/1/2/3/4/5/6 PCP0 PPCA0 PADC0 PWADC0 R/W ...
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... C8051T610/1/2/3/4/5/6/7 16.3. External Interrupts INT0 and INT1 The INT0 and INT1 external interrupt sources are configurable as active high or low, edge or level sensi- tive. The IN0PL (INT0 Polarity) and IN1PL (INT1 Polarity) bits in the IT01CF register select active high or active low; the IT0 and IT1 bits in TCON (Section “25.1. Timer 0 and Timer 1” on page 172) select level or edge sensitive ...
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... Port pin via the Crossbar. The Crossbar will not assign the Port pin to a peripheral configured to skip the selected pin. 000: Select P0.0 001: Select P0.1 010: Select P0.2 011: Select P0.3 100: Select P0.4 101: Select P0.5 110: Select P0.6 111: Select P0.7 C8051T610/1/2/3/4/5/6 IN0PL R/W R Function Rev 1 ...
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... Refer to the “C2 Interface Specification” available at http://www.silabs.com for details on com- municating via the C2 interface. Section “27. C2 Interface” on page 208 has information about C2 register addresses for the C8051T610/1/2/3/4/5/6/7. 17.1.1. EPROM Write Procedure 1. Reset the device using the RST pin. ...
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... Reset the device: Write 0x02 and then 0x00 to the DEVCTL register. 17.2. Security Options The C8051T610/1/2/3/4/5/6/7 devices provide security options to prevent unauthorized viewing of proprie- tary program code and constants. A security byte in EPROM address space can be used to lock the pro- gram memory from being read or written across the C2 interface. When read, the RDLOCK and WRLOCK bits in register EPSTAT will indicate the lock status of the location currently addressed by EPADDR. Table 17.1 shows the security byte decoding. See Section “ ...
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... C8051T610/1/2/3/4/5/6/7 17.3. Program Memory CRC A CRC engine is included on-chip which provides a means of verifying EPROM contents once the device has been programmed. The CRC engine is available for EPROM verification even if the device is fully read and write locked, allowing for verification of code contents at any time. ...
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... Power Control Register (PCON) used to control the C8051T610/1/2/3/4/5/6/7's stop and idle power management modes. Although the C8051T610/1/2/3/4/5/6/7 has idle and stop modes available, more control over the device power can be achieved by enabling/disabling individual peripherals as needed. Each analog peripheral can be disabled when not in use and placed in low power mode. Digital peripherals, such as timers or serial buses, draw little power when they are not in use ...
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... C8051T610/1/2/3/4/5/6/7 18.2. Stop Mode Setting the Stop Mode Select bit (PCON.1) causes the controller core to enter stop mode as soon as the instruction that sets the bit completes execution. In stop mode the internal oscillator, CPU, and all digital peripherals are stopped; the state of the external oscillator circuit is not affected. Each analog peripheral (including the external oscillator circuit) may be shut down individually prior to entering stop mode ...
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... IDLE Idle Mode Select. Setting this bit will place the CIP-51 in Idle mode. This bit will always be read CPU goes into Idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts, Serial Ports, and Analog Peripherals are still active.) C8051T610/1/2/3/4/5/6 GF[5:0] ...
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... C8051T610/1/2/3/4/5/6/7 19. Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: CIP-51 halts program execution Special Function Registers (SFRs) are initialized to their defined reset values External Port pins are forced to a known state ...
Page 101
... The V is enabled following a power-on reset. V RST RST Logic HIGH Logic LOW Power-On Reset Figure 19.2. Power-On and V C8051T610/1/2/3/4/5/6/7 ramps from ramp time is 1 ms; slower ramp times may DD reaches the V level. For ramp times less than DD RST ) is typically less than 0.3 ms. ...
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... C8051T610/1/2/3/4/5/6/7 19.2. Power-Fail Reset/V DD When a power-down transition or power irregularity causes V monitor will drive the RST pin low and hold the CIP- reset state (see Figure 19.2). When level above V , the CIP-51 will be released from the reset state. Note that even though internal data ...
Page 103
... After a MCD reset, the MCDRSF flag (RSTSRC.2) will read 1, signifying the MCD as the reset source; otherwise, this bit reads 0. Writing the MCDRSF bit enables the Missing Clock Detector; writ- ing a 0 disables it. The state of the RST pin is unaffected by this reset. C8051T610/1/2/3/4/5/6/7 Monitor Control DD ...
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... C8051T610/1/2/3/4/5/6/7 19.5. Comparator0 Reset Comparator0 can be configured as a reset source by writing the C0RSEF flag (RSTSRC.5). Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on chatter on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non- inverting input voltage (on CP0+) is less than the inverting input voltage (on CP0-), the device is put into the reset state. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read 1 signifying Comparator0 as the reset source ...
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... WDTRSF Watchdog Timer Reset Flag. N/A 2 MCDRSF Missing Clock Detector Enable and Flag. 1 PORSF Power-On/V Monitor DD Reset Flag, and V Reset Enable. 0 PINRSF HW Pin Reset Flag. Note: Do not use read-modify-write operations on this register C8051T610/1/2/3/4/5/6 SWRSF WDTRSF MCDRSF R/W R/W R Varies Varies Write Don’t care. N/A ...
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... C8051T610/1/2/3/4/5/6/7 20. Oscillators and Clock Selection C8051T610/1/2/3/4/5/6/7 devices include a programmable internal high-frequency oscillator and an exter- nal oscillator drive circuit. The internal high-frequency oscillator can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as shown in Figure 20.1. The system clock can be sourced by the external oscillator circuit or the internal oscillator. The internal oscillator also offers a selectable post- scaling feature ...
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... Bit Name 7:1 Unused Unused. Read = 0000000b; Write = Don’t Care 0 CLKSL0 System Clock Source Select Bit. 0: SYSCLK derived from the Internal High-Frequency Oscillator and scaled per the IFCN bits in register OSCICN. 1: SYSCLK derived from the External Oscillator circuit. C8051T610/1/2/3/4/5/6 Function Rev 1 ...
Page 108
... The internal oscillator period can be adjusted via the OSCICL register as defined by SFR Definition 20.2. On C8051T610/1/2/3/4/5/6/7 devices, OSCICL is factory calibrated to obtain a 24.5 MHz base frequency. The system clock may be derived from the programmed internal oscillator divided defined by the IFCN bits in register OSCICN ...
Page 109
... IFCN[1:0] Internal H-F Oscillator Frequency Divider Control Bits. 00: SYSCLK derived from Internal H-F Oscillator divided by 8. 01: SYSCLK derived from Internal H-F Oscillator divided by 4. 10: SYSCLK derived from Internal H-F Oscillator divided by 2. 11: SYSCLK derived from Internal H-F Oscillator divided by 1. C8051T610/1/2/3/4/5/6 ...
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... C8051T610/1/2/3/4/5/6/7 20.3. External Oscillator Drive Circuit The external oscillator circuit may drive an external capacitor or RC network. A CMOS clock may also pro- vide a clock input. In RC, capacitor, or CMOS clock configuration, the clock source should be wired to the EXTCLK pin as shown in Figure 20.1. The type of external oscillator must be selected in the OSCXCN reg- ister, and the frequency control bits (XFCN) must be selected appropriately (see SFR Definition 20 ...
Page 111
... MHz 110 1.6 MHz f 3.2 MHz 111 C8051T610/1/2/3/4/5/6 R Function C Mode K Factor = 0 ...
Page 112
... C8051T610/1/2/3/4/5/6/7 20.3.1. External RC Example network is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 20.1, “RC Mode”. The capacitor should be no greater than 100 pF; however for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout. To deter- mine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, first select the RC network value to produce the desired frequency of oscillation, according to Equation 20 ...
Page 113
... Digital and analog resources are available through 29 I/O pins organized as three byte-wide ports and one 5-bit-wide port on the C8051T610/2/4. The C8051T611/3/5 devices have 25 I/O pins available, organized as three byte-wide ports and one 1-bit-wide port. The C8051T616/7 have 21 I/O pins available on a single byte-wide port, two 6-bit-wide ports, and a 1-bit-wide port ...
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... C8051T610/1/2/3/4/5/6/7 21.1. Port I/O Modes of Operation Port pins use the Port I/O cell shown in Figure 21.2. Each Port I/O cell can be configured by software for analog I/O or digital I/O using the PnMDIN registers. On reset, all Port I/O cells default to a high impedance state with weak pull-ups enabled until the Crossbar is enabled (XBARE = 1) ...
Page 115
... Port pin when the supply voltage is between (VDD + 0.6 V) and (VDD + 1.0 V). Once the Port pin voltage increases beyond this range, the current flowing into the Port pin is minimal. C8051T610/1/2/3/4/5/6/7 VDD VDD ...
Page 116
... C8051T610/1/2/3/4/5/6/7 21.2. Assigning Port I/O Pins to Analog and Digital Functions Port I/O pins can be assigned to various analog, digital, and external interrupt functions. The Port pins assigned to analog functions should be configured for analog I/O, and Port pins assigned to digital or exter- nal interrupt functions should be configured for digital I/O. ...
Page 117
... Important Note: The SPI can be operated in either 3-wire or 4-wire modes, pending the state of the NSSMD1–NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not be routed to a Port pin. C8051T610/1/2/3/4/5/6/7 Potentially Assignable Port Pins P0.0–P0.7 P0.0–P0.7 Rev 1 ...
Page 118
... C8051T610/1/2/3/4/5/6/7 Port P0 Pin Number Special Function Signals TX0 RX0 SCK MISO MOSI NSS* SDA SCL CP0 CP0A CP1 CP1A SYSCLK CEX0 CEX1 CEX2 CEX3 CEX4 ECI Pin Skip Settings P0SKIP Pins P0.0-P2.3 are capable of being assigned to crossbar peripherals. The crossbar peripherals are assigned in priority order from top to bottom, according to this diagram ...
Page 119
... TX0 is assigned to P0 RX0 is assigned to P0 SDA and SCL are assigned to P0.0 and P0.1, respectively SYSCLK is assigned to P0.2 All unassigned pins can be used as GPIO or for other non-crossbar functions. Figure 21.4. Priority Crossbar Decoder Example Skipped Pins C8051T610/1/2/3/4/5/6 P1SKIP P2SKIP Rev 1.0 P2 119 ...
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... C8051T610/1/2/3/4/5/6/7 Port P0 Pin Number Special Function Signals TX0 RX0 SCK MISO MOSI NSS* SDA SCL CP0 CP0A CP1 CP1A SYSCLK CEX0 CEX1 CEX2 CEX3 CEX4 ECI Pin Skip Settings P0SKIP In this example, the crossbar is configured to assign the UART TX0 and RX0 signals, the SMBus signals, and the SYSCLK signal ...
Page 121
... Table alternative, the Configuration Wizard utility available at the Silicon Labs web site will deter- mine the Port I/O pin-assignments based on the XBRn register settings. The Crossbar must be enabled to use Port pins as standard Port I/O in output mode. Port output drivers are disabled while the Crossbar is disabled. C8051T610/1/2/3/4/5/6/7 Rev 1.0 121 ...
Page 122
... C8051T610/1/2/3/4/5/6/7 SFR Definition 21.1. XBR0: Port I/O Crossbar Register 0 Bit 7 6 CP1AE CP1E Name R/W R/W Type 0 0 Reset SFR Address = 0xE1 Bit Name 7 CP1AE Comparator1 Asynchronous Output Enable. 0: Asynchronous CP1 unavailable at Port pin. 1: Asynchronous CP1 routed to Port pin. 6 CP1E Comparator1 Output Enable. ...
Page 123
... Unused Unused. Read = 0b; Write = Don’t Care. 1:0 PCA0ME[1:0] PCA Module I/O Enable Bits. 00: All PCA I/O unavailable at Port pins. 01: CEX0 routed to Port pin. 10: CEX0, CEX1 routed to Port pins. 11: CEX0, CEX1, CEX2 routed to Port pins. C8051T610/1/2/3/4/5/6 T1E T0E ECIE R/W R/W ...
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... C8051T610/1/2/3/4/5/6/7 21.5. Special Function Registers for Accessing and Configuring Port I/O All Port I/O are accessed through corresponding special function registers (SFRs) that are both byte addressable and bit addressable. When writing to a Port, the value written to the SFR is latched to main- tain the output data value at each pin ...
Page 125
... Name Type 0 0 Reset SFR Address = 0xA4 Bit Name 7:0 P0MDOUT[7:0] Output Configuration Bits for P0.7–P0.0 (respectively). These bits are ignored if the corresponding bit in register P0MDIN is logic 0. 0: Corresponding P0.n pin is open-drain. 1: Corresponding P0.n pin is push-pull. C8051T610/1/2/3/4/5/6 P0MDIN[7:0] R Function P0MDOUT[7:0] ...
Page 126
... C8051T610/1/2/3/4/5/6/7 SFR Definition 21.6. P0SKIP: Port 0 Skip Bit 7 6 Name Type 0 0 Reset SFR Address = 0xD4 Bit Name 7:0 P0SKIP[7:0] Port 0 Crossbar Skip Enable Bits. These bits select Port 0 pins to be skipped by the Crossbar Decoder. Port pins used for analog, special functions or GPIO should be skipped by the Crossbar. ...
Page 127
... P1MDOUT[7:0] Output Configuration Bits for P1.7–P1.0 (respectively). These bits are ignored if the corresponding bit in register P1MDIN is logic 0. 0: Corresponding P1.n pin is open-drain. 1: Corresponding P1.n pin is push-pull. Note: P1.6 and P1.7 are not connected to external pins on the C8051T616/7 devices. C8051T610/1/2/3/4/5/6 P1MDIN[7:0] ...
Page 128
... C8051T610/1/2/3/4/5/6/7 SFR Definition 21.10. P1SKIP: Port 1 Skip Bit 7 6 Name Type 0 0 Reset SFR Address = 0xD5 Bit Name 7:0 P1SKIP[7:0] Port 1 Crossbar Skip Enable Bits. These bits select Port 1 pins to be skipped by the Crossbar Decoder. Port pins used for analog, special functions or GPIO should be skipped by the Crossbar. ...
Page 129
... Name Type 0 0 Reset SFR Address = 0xA6 Bit Name 7:0 P2MDOUT[7:0] Output Configuration Bits for P2.7–P2.0 (respectively). 0: Corresponding P2.n pin is open-drain. 1: Corresponding P2.n pin is push-pull. Note: P2.6 and P2.7 are not connected to external pins on the C8051T616/7 devices. C8051T610/1/2/3/4/5/6 P2MDIN[7:0] R Function 5 4 ...
Page 130
... C8051T610/1/2/3/4/5/6/7 SFR Definition 21.14. P2SKIP: Port 2 Skip Bit 7 6 Name R Type 0 0 Reset SFR Address = 0xD6 Bit Name 7:4 Unused Unused. Read = 0000b; Write = Don’t Care. 3:0 P2SKIP[3:0] Port 2 Crossbar Skip Enable Bits. These bits select Port 2 pins to be skipped by the Crossbar Decoder. Port pins used for analog, special functions or GPIO should be skipped by the Crossbar ...
Page 131
... Unused Unused. Read = 000b; Write = Don’t Care. 4:0 P3MDOUT[4:0] Output Configuration Bits for P3.4–P3.0 (respectively). 0: Corresponding P3.n pin is open-drain. 1: Corresponding P3.n pin is push-pull. Note: P3.1-P3.4 are not connected to external pins on the C8051T611/3/5 and C8051T616/7 devices. C8051T610/1/2/3/4/5/6 P3MDIN[4:0] R/W 0 ...
Page 132
... C8051T610/1/2/3/4/5/6/7 22. SMBus The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specification, version 1.1, and compatible with the I the interface by the system controller are byte oriented with the SMBus interface autonomously controlling the serial transfer of the data. Data can be transferred 1/20th of the system clock as a master or slave (this can be faster than allowed by the SMBus specification, depending on the system clock used) ...
Page 133
... Figure 22.3). If the receiving device does not ACK, the transmitting device will read a NACK (not acknowl- edge), which is a high SDA during a high SCL. The direction bit (R/W) occupies the least-significant bit position of the address byte. The direction bit is set to logic 1 to indicate a "READ" operation and cleared to logic 0 to indicate a "WRITE" operation. C8051T610/1/2/3/4/5/6/7 VDD = 5V VDD = 3V Slave ...
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... C8051T610/1/2/3/4/5/6/7 All transactions are initiated by a master, with one or more addressed slave devices as the target. The master generates the START condition and then transmits the slave address and direction bit. If the trans- action is a WRITE operation from the master to the slave, the master transmits the data a byte at a time waiting for an ACK from the slave at the end of each byte ...
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... NACK all received addresses and will not generate any slave interrupts. When the INH bit is set, all slave events will be inhibited following the next START (interrupts will continue for the duration of the current transfer). C8051T610/1/2/3/4/5/6/7 Rev 1.0 135 ...
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... C8051T610/1/2/3/4/5/6/7 Table 22.1. SMBus Clock Source Selection SMBCS1 The SMBCS1–0 bits select the SMBus clock source, which is used only when operating as a master or when the Free Timeout detection is enabled. When operating as a master, overflows from the selected source determine the absolute minimum SCL low and high times as defined in Equation 22.1. Note that the selected clock source may be shared by other peripherals so long as the timer is left running at all times ...
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... SMBus Free Timeout detection can be enabled by setting the SMBFTE bit. When this bit is set, the bus will be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods (see Figure 22.4). C8051T610/1/2/3/4/5/6/7 Minimum SDA Hold Time – 4 system clocks ...
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... C8051T610/1/2/3/4/5/6/7 SFR Definition 22.1. SMB0CF: SMBus Clock/Configuration Bit 7 6 ENSMB INH Name R/W R/W Type 0 0 Reset SFR Address = 0xC1 Bit Name 7 ENSMB SMBus Enable. This bit enables the SMBus interface when set to 1. When enabled, the interface constantly monitors the SDA and SCL pins. ...
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... Important Note About the SI Bit: The SMBus interface is stalled while SI is set; thus SCL is held low, and the bus is stalled until software clears SI. Table 22.3 lists all sources for hardware changes to the SMB0CN bits. Refer to Table 22.4 for SMBus sta- tus decoding using the SMB0CN register. C8051T610/1/2/3/4/5/6/7 Rev 1.0 139 ...
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... C8051T610/1/2/3/4/5/6/7 SFR Definition 22.2. SMB0CN: SMBus Control Bit 7 6 MASTER TXMODE Name R R Type 0 0 Reset SFR Address = 0xC0; Bit-Addressable Bit Name Description 7 MASTER SMBus Master/Slave Indicator. This read-only bit indicates when the SMBus is operating as a master. 6 TXMODE SMBus Transmit Mode Indicator ...
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... A byte has been transmitted and an ACK/NACK received. SI A byte has been received. A START or repeated START followed by a slave address + R/W has been received. A STOP has been received. C8051T610/1/2/3/4/5/6/7 Cleared by Hardware When: A STOP is generated. Arbitration is lost. A START is detected. Arbitration is lost. ...
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... C8051T610/1/2/3/4/5/6/7 22.4.3. Data Register The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received. Software may safely read or write to the data register when the SI flag is set. Software should not attempt to access the SMB0DAT register when the SMBus is enabled and the SI flag is cleared to logic 0, as the interface may be in the process of shifting a byte of data into or out of the register ...
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... Notice that all of the “data byte transferred” interrupts occur after the ACK cycle in this mode. S SLA W Received by SMBus Interface Transmitted by SMBus Interface Figure 22.5. Typical Master Write Sequence C8051T610/1/2/3/4/5/6/7 A Data Byte A Data Byte Interrupt Locations S = START P = STOP A = ACK W = WRITE SLA = Slave Address Rev 1 ...
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... C8051T610/1/2/3/4/5/6/7 22.5.2. Read Sequence (Master) During a read sequence, an SMBus master reads data from a slave device. The master in this transfer will be a transmitter during the address byte, and a receiver during all data bytes. The SMBus interface gener- ates the START condition and transmits the first byte containing the address of the target slave and the data direction bit ...
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... Two received data bytes are shown, though any number of bytes may be received. Notice that the ‘data byte transferred’ interrupts occur before the ACK. S SLA W Received by SMBus Interface Transmitted by SMBus Interface Figure 22.7. Typical Slave Write Sequence C8051T610/1/2/3/4/5/6/7 A Data Byte A Data Byte Interrupt Locations S = START P = STOP A = ACK W = WRITE SLA = Slave Address Rev 1 ...
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... C8051T610/1/2/3/4/5/6/7 22.5.4. Read Sequence (Slave) During a read sequence, an SMBus master reads data from a slave device. The slave in this transfer will be a receiver during the address byte, and a transmitter during all data bytes. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START followed by a slave address and direction bit (READ in this case) is received ...
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... ACK received. A master data byte was 1000 received; ACK requested. C8051T610/1/2/3/4/5/6/7 Typical Response Options Load slave address + R/W into SMB0DAT. Set STA to restart transfer. Abort transfer. Load next data byte into SMB0DAT. End transfer with STOP. End transfer with STOP and start another transfer ...
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... C8051T610/1/2/3/4/5/6/7 Table 22.4. SMBus Status Decoding Values Read Current SMbus State A slave byte was transmitted NACK received. A slave byte was transmitted; 0100 ACK received. A Slave byte was transmitted error detected. An illegal STOP or bus error 0101 was detected while a Slave Transmission was in progress. ...
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... CPU vectors to the interrupt service routine. They must be cleared manually by software, allowing software to determine the cause of the UART0 interrupt (transmit complete or receive complete). Write to SBUF UART Baud Rate Generator Figure 23.1. UART0 Block Diagram C8051T610/1/2/3/4/5/6/7 SFR Bus TB8 SBUF SET (TX Shift ...
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... C8051T610/1/2/3/4/5/6/7 23.1. Enhanced Baud Rate Generation The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 23.2), which is not user- accessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates. ...
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... RI0 flag is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not be set. An interrupt will occur if enabled when either TI0 or RI0 is set. MARK START D0 D1 BIT SPACE BIT TIMES BIT SAMPLING Figure 23.4. 8-Bit UART Timing Diagram C8051T610/1/2/3/4/5/6/7 TX RS-232 RS-232 C8051xxxx LEVEL RX XLTR ...
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... C8051T610/1/2/3/4/5/6/7 23.2.2. 9-Bit UART 9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programma- ble ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB80 (SCON0.3), which is assigned by user software. It can be assigned the value of the parity flag (bit P in reg- ister PSW) for error detection, or used in multiprocessor communications ...
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... Master Slave Device Device Figure 23.6. UART Multi-Processor Mode Interconnect Diagram C8051T610/1/2/3/4/5/6/7 Slave Slave Device Device Rev 1.0 V+ ...
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... C8051T610/1/2/3/4/5/6/7 SFR Definition 23.1. SCON0: Serial Port 0 Control Bit 7 6 Name S0MODE R/W R Type 0 1 Reset SFR Address = 0x98; Bit-Addressable Bit Name 7 S0MODE Serial Port 0 Operation Mode. Selects the UART0 Operation Mode. 0: 8-bit UART with Variable Baud Rate. 1: 9-bit UART with Variable Baud Rate. ...
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... This SFR accesses two registers; a transmit shift register and a receive latch register. When data is written to SBUF0, it goes to the transmit shift register and is held for serial transmission. Writing a byte to SBUF0 initiates the transmission. A read of SBUF0 returns the contents of the receive latch. C8051T610/1/2/3/4/5/6 ...
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... C8051T610/1/2/3/4/5/6/7 Table 23.1. Timer Settings for Standard Baud Rates Using The Internal 24.5 MHz Oscillator Target Baud Rate % Error Baud Rate (bps) 230400 –0.32% 115200 –0.32% 57600 0.15% 28800 –0.32% 14400 0.15% 9600 –0.32% 2400 –0.32% 1200 0.15% Notes: – 1. SCA1 SCA0 and T1M bit definitions can be found Don’ ...
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... I/O pins can be used to select multiple slave devices in master mode. SPI0CKR Clock Divide SYSCLK Logic Transmit Data Buffer 7 6 Receive Data Buffer Write SPI0DAT SFR Bus Figure 24.1. SPI Block Diagram C8051T610/1/2/3/4/5/6/7 SFR Bus SPI0CFG SPI0CN SPI CONTROL LOGIC Data Path Pin Interface Control Control MOSI Tx Data SPI0DAT SCK ...
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... C8051T610/1/2/3/4/5/6/7 24.1. Signal Descriptions The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below. 24.1.1. Master Out, Slave In (MOSI) The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices used to serially transfer data from the master to the slave. This signal is an output when SPI0 is operat- ing as a master and an input when SPI0 is operating as a slave ...
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... NSS is controlled (in software) with the bit NSSMD0 (SPI0CN.2). Additional slave devices can be addressed using general-purpose I/O pins. Figure 24.4 shows a connection diagram for a master device in 4-wire master mode and two slave devices. Master Device 1 Figure 24.2. Multiple-Master Mode Connection Diagram C8051T610/1/2/3/4/5/6/7 NSS GPIO MISO MISO Master ...
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... C8051T610/1/2/3/4/5/6/7 Master Device Figure 24.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Master Device GPIO Figure 24.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection 24.3. SPI0 Slave Mode Operation When SPI0 is enabled and not configured as a master, it will operate as a SPI slave slave, bytes are shifted in through the MOSI pin and out through the MISO pin by a master device controlling the SCK sig- nal ...
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... SPI slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency. This is provided that the master issues SCK, NSS, and the serial input data synchronously with the slave’s system clock. C8051T610/1/2/3/4/5/6/7 Rev 1.0 161 ...
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... C8051T610/1/2/3/4/5/6/7 SCK (CKPOL=0, CKPHA=0) SCK (CKPOL=0, CKPHA=1) SCK (CKPOL=1, CKPHA=0) SCK (CKPOL=1, CKPHA=1) MISO/MOSI MSB NSS (Must Remain High in Multi-Master Mode) Figure 24.5. Master Mode Data/Clock Timing SCK (CKPOL=0, CKPHA=0) SCK (CKPOL=1, CKPHA=0) MOSI MSB MISO MSB NSS (4-Wire Mode) Figure 24.6. Slave Mode Data/Clock Timing (CKPHA = 0) ...
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... SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate Register. The four special function registers related to the operation of the SPI0 Bus are described in the following figures. C8051T610/1/2/3/4/5/6/7 Bit 6 Bit 5 Bit 4 ...
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... C8051T610/1/2/3/4/5/6/7 SFR Definition 24.1. SPI0CFG: SPI0 Configuration Bit 7 6 SPIBSY MSTEN CKPHA Name R R/W Type 0 0 Reset SFR Address = 0xA1 Bit Name 7 SPIBSY SPI Busy. This bit is set to logic 1 when a SPI transfer is in progress (master or slave mode). 6 MSTEN Master Mode Enable. ...
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... This bit will be set to logic 0 when new data has been written to the transmit buffer. When data in the transmit buffer is transferred to the SPI shift register, this bit will be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer. 0 SPIEN SPI0 Enable. 0: SPI disabled. 1: SPI enabled. C8051T610/1/2/3/4/5/6 RXOVRN NSSMD[1:0] R/W R/W ...
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... C8051T610/1/2/3/4/5/6/7 SFR Definition 24.3. SPI0CKR: SPI0 Clock Rate Bit 7 6 Name Type 0 0 Reset SFR Address = 0xA2 Bit Name 7:0 SCR[7:0] SPI0 Clock Rate. These bits determine the frequency of the SCK output when the SPI0 module is configured for master mode operation. The SCK clock frequency is a divided ver- ...
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... SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 24.8. SPI Master Timing (CKPHA = 0) SCK* T MCKH T MIS MISO MOSI * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 24.9. SPI Master Timing (CKPHA = 1) C8051T610/1/2/3/4/5/6/7 T MCKL T T MIS MIH T MCKL T MIH Rev 1 ...
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... C8051T610/1/2/3/4/5/6/7 NSS T SE SCK* T CKH MOSI T SEZ MISO * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 24.10. SPI Slave Timing (CKPHA = 0) NSS T SE SCK* T CKH T SIS MOSI T T SOH SEZ MISO * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. ...
Page 169
... MOSI Valid to SCK Sample Edge SIS T SCK Sample Edge to MOSI Change SIH T SCK Shift Edge to MISO Change SOH Last SCK Edge to MISO Change T SLH (CKPHA = 1 ONLY) Note equal to one period of the device system clock (SYSCLK). SYSCLK C8051T610/1/2/3/4/5/6/7 Min SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK — ...
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... C8051T610/1/2/3/4/5/6/7 25. Timers Each MCU includes four counter/timers: two are 16-bit counter/timers compatible with those found in the standard 8051, and two are 16-bit auto-reload timer for use with the ADC, SMBus, or for general purpose use. These timers can be used to measure time intervals, count external events and generate periodic interrupt requests ...
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... Counter/Timer 0 uses the system clock. 1:0 SCA[1:0] Timer 0/1 Prescale Bits. These bits control the Timer 0/1 Clock Prescaler: 00: System clock divided by 12 01: System clock divided by 4 10: System clock divided by 48 11: External clock divided by 8 (synchronized with the system clock) C8051T610/1/2/3/4/5/6 T2ML T1M R/W R/W ...
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... C8051T610/1/2/3/4/5/6/7 25.1. Timer 0 and Timer 1 Each timer is implemented as a 16-bit register accessed as two separate bytes: a low byte (TL0 or TL1) and a high byte (TH0 or TH1). The Counter/Timer Control register (TCON) is used to enable Timer 0 and Timer 1 as well as indicate status. Timer 0 interrupts can be enabled by setting the ET0 bit in the IE regis- ter (Section “ ...
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... XOR /INT0 Figure 25.1. T0 Mode 0 Block Diagram 25.1.2. Mode 1: 16-bit Counter/Timer Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The coun- ter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0. C8051T610/1/2/3/4/5/6/7 TMOD IT01CF ...
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... C8051T610/1/2/3/4/5/6/7 25.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start value. TL0 holds the count and TH0 holds the reload value. When the counter in TL0 overflows from all ones to 0x00, the timer overflow flag TF0 in the TCON register is set and the counter in TL0 is reloaded from TH0 ...
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... While Timer 0 is operating in Mode 3, Timer 1 run control is handled through its mode set- tings. To run Timer 1 while Timer Mode 3, set the Timer 1 Mode disable Timer 1, configure it for Mode 3. T0M Pre-scaled Clock 0 SYSCLK 1 T0 Crossbar GATE0 IN0PL XOR /INT0 Figure 25.3. T0 Mode 3 Block Diagram C8051T610/1/2/3/4/5/6/7 TMOD ...
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... C8051T610/1/2/3/4/5/6/7 SFR Definition 25.2. TCON: Timer Control Bit 7 6 TF1 TR1 Name R/W R/W Type 0 0 Reset SFR Address = 0x88; Bit-Addressable Bit Name 7 TF1 Timer 1 Overflow Flag. Set hardware when Timer 1 overflows. This flag can be cleared by software but is automatically cleared when the CPU vectors to the Timer 1 interrupt service routine ...
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... Counter: Timer 0 incremented by high-to-low transitions on external pin (T0). 1:0 T0M[1:0] Timer 0 Mode Select. These bits select the Timer 0 operation mode. 00: Mode 0, 13-bit Counter/Timer 01: Mode 1, 16-bit Counter/Timer 10: Mode 2, 8-bit Counter/Timer with Auto-Reload 11: Mode 3, Two 8-bit Counter/Timers C8051T610/1/2/3/4/5/6 T1M[1:0] GATE0 C/T0 R/W R/W R/W ...
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... C8051T610/1/2/3/4/5/6/7 SFR Definition 25.4. TL0: Timer 0 Low Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0x8A Bit Name 7:0 TL0[7:0] Timer 0 Low Byte. The TL0 register is the low byte of the 16-bit Timer 0. SFR Definition 25.5. TL1: Timer 1 Low Byte Bit ...
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... The TH0 register is the high byte of the 16-bit Timer 0. SFR Definition 25.7. TH1: Timer 1 High Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0x8D Bit Name 7:0 TH1[7:0] Timer 1 High Byte. The TH1 register is the high byte of the 16-bit Timer 1. C8051T610/1/2/3/4/5/6 TH0[7:0] R Function TH1[7:0] R ...
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... C8051T610/1/2/3/4/5/6/7 25.2. Timer 2 Timer 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T2SPLIT bit (TMR2CN.3) defines the Timer 2 operation mode. Timer 2 may be clocked by the system clock, the system clock divided by 12, or the external oscillator source divided by 8 ...
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... TF2L flags to determine the source of the Timer 2 interrupt. The TF2H and TF2L interrupt flags are not cleared by hardware and must be manually cleared by software. T2XCLK SYSCLK / External Clock / SYSCLK 1 0 Figure 25.5. Timer 2 8-Bit Mode Block Diagram C8051T610/1/2/3/4/5/6/7 T2ML T2XCLK Reload T2MH TMR2RLH TCLK ...
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... C8051T610/1/2/3/4/5/6/7 SFR Definition 25.8. TMR2CN: Timer 2 Control Bit 7 6 TF2H TF2L TF2LEN Name R/W R/W Type 0 0 Reset SFR Address = 0xC8; Bit-Addressable Bit Name 7 TF2H Timer 2 High Byte Overflow Flag. Set by hardware when the Timer 2 high byte overflows from 0xFF to 0x00 bit mode, this will occur when Timer 2 overflows from 0xFFFF to 0x0000 ...
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... Name Type 0 0 Reset SFR Address = 0xCC Bit Name 7:0 TMR2L[7:0] Timer 2 Low Byte. In 16-bit mode, the TMR2L register contains the low byte of the 16-bit Timer bit mode, TMR2L contains the 8-bit low byte timer value. C8051T610/1/2/3/4/5/6 TMR2RLL[7:0] R Function TMR2RLH[7:0] ...
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... C8051T610/1/2/3/4/5/6/7 SFR Definition 25.12. TMR2H Timer 2 High Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0xCD Bit Name 7:0 TMR2H[7:0] Timer 2 Low Byte. In 16-bit mode, the TMR2H register contains the high byte of the 16-bit Timer bit mode, TMR2H contains the 8-bit high byte timer value. ...
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... T3XCLK T3ML SYSCLK / External Clock / 8 1 SYSCLK 1 Figure 25.6. Timer 3 16-Bit Mode Block Diagram C8051T610/1/2/3/4/5/6/7 To SMBus TL3 Overflow TCLK TR3 TMR3L TMR3H TMR3RLL TMR3RLH Reload Rev 1.0 To ADC, ...
Page 186
... C8051T610/1/2/3/4/5/6/7 25.3.2. 8-bit Timers with Auto-Reload When T3SPLIT is set, Timer 3 operates as two 8-bit timers (TMR3H and TMR3L). Both 8-bit timers oper- ate in auto-reload mode as shown in Figure 25.7. TMR3RLL holds the reload value for TMR3L; TMR3RLH holds the reload value for TMR3H. The TR3 bit in TMR3CN handles the run control for TMR3H. TMR3L is always running when configured for 8-bit Mode ...
Page 187
... Timer 3 Clock Select bits (T3MH and T3ML in register CKCON) may still be used to select between the external clock and the system clock for either timer. 0: Timer 3 clock is the system clock divided by 12. 1: Timer 3 clock is the external clock divided by 8 (synchronized with SYSCLK). C8051T610/1/2/3/4/5/6 ...
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... C8051T610/1/2/3/4/5/6/7 SFR Definition 25.14. TMR3RLL: Timer 3 Reload Register Low Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0x92 Bit Name 7:0 TMR3RLL[7:0] Timer 3 Reload Register Low Byte. TMR3RLL holds the low byte of the reload value for Timer 3. SFR Definition 25.15. TMR3RLH: Timer 3 Reload Register High Byte ...
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... Name Type 0 0 Reset SFR Address = 0x95 Bit Name 7:0 TMR3H[7:0] Timer 3 Low Byte. In 16-bit mode, the TMR3H register contains the high byte of the 16-bit Timer bit mode, TMR3H contains the 8-bit high byte timer value. C8051T610/1/2/3/4/5/6 TMR3H[7:0] R Function Rev 1.0 ...
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... C8051T610/1/2/3/4/5/6/7 26. Programmable Counter Array The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer and five 16-bit capture/compare modules. Each capture/compare module has its own associated I/O line (CEXn) which is routed through the Crossbar to Port I/O when enabled ...
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... ECI 011 SYSCLK 100 External Clock/8 101 Figure 26.2. PCA Counter/Timer Block Diagram C8051T610/1/2/3/4/5/6/7 Timebase System clock divided by 12 System clock divided by 4 Timer 0 overflow High-to-low transitions on ECI (max rate = system clock divided by 4) System clock External oscillator source divided by 8 ...
Page 192
... C8051T610/1/2/3/4/5/6/7 26.2. PCA0 Interrupt Sources Figure 26.3 shows a diagram of the PCA interrupt tree. There are six independent event flags that can be used to generate a PCA0 interrupt. They are: the main PCA counter overflow flag (CF), which is set upon a 16-bit overflow of the PCA0 counter and the individual flags for each PCA channel (CCF0, CCF1, CCF2, CCF3, and CCF4), which are set according to the operation mode of that module ...
Page 193
... B = When set to 0, the digital comparator is off. For high speed and frequency output modes, the associated pin will not toggle. In any of the PWM modes, this generates a 0% duty cycle (output = 0 When set, a match event will cause the CCFn flag for the associated channel to be set. C8051T610/1/2/3/4/5/6/7 Bit Number ...
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... C8051T610/1/2/3/4/5/6/7 26.3.1. Edge-triggered Capture Mode In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA coun- ter/timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transi- tion that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge), or either transition (positive or negative edge) ...
Page 195
... Writing to PCA0CPLn clears the ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1. Write to PCA0CPLn 0 ENB Reset Write to PCA0CPHn ENB 1 PCA0CPMn Enable Figure 26.5. PCA Software Timer Mode Diagram C8051T610/1/2/3/4/5/6/7 PCA0CPLn PCA0CPHn Match 16-bit Comparator PCA PCA0L PCA0H Timebase Rev 1.0 PCA Interrupt PCA0CN 195 ...
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... C8051T610/1/2/3/4/5/6/7 26.3.3. High-Speed Output Mode In High-Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1. An interrupt request is generated if the CCFn interrupt for that module is enabled ...
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... ENB Reset PCA0CPMn Write PCA0CPHn ENB Figure 26.7. PCA Frequency Output Mode C8051T610/1/2/3/4/5/6/7 F PCA ---------------------------------------- - F = CEXn 2 PCA0CPHn E C PCA0CPLn 8-bit Adder C F Adder n Enable Toggle x 8-bit match Enable Comparator PCA Timebase PCA0L Rev 1.0 PCA0CPHn TOGn 0 CEXn Crossbar Port I/O 1 197 ...
Page 198
... C8051T610/1/2/3/4/5/6/7 26.3.5. 8-bit Pulse Width Modulator Mode The duty cycle of the PWM output signal in 8-bit PWM mode is varied using the module's PCA0CPLn cap- ture/compare register. When the value in the low byte of the PCA counter/timer (PCA0L) is equal to the value in PCA0CPLn, the output on the CEXn pin will be set. When the count value in PCA0L overflows, the CEXn output will be reset (see Figure 26.8). Also, when the counter/timer low byte (PCA0L) overflows from 0xFF to 0x00, PCA0CPLn is reloaded automatically with the value stored in the module’ ...
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... PCA0CPLn 0 ENB Reset Write to PCA0CPHn ENB 1 PCA0CPMn PCA Timebase Figure 26.9. PCA 16-Bit PWM Mode C8051T610/1/2/3/4/5/6/7 65536 PCA0CPn – ---------------------------------------------------- - = 65536 PCA0CPHn PCA0CPLn match Enable 16-bit Comparator S R PCA0H PCA0L Overflow Rev 1.0 CEXn SET Q Crossbar Port I/O Q CLR 199 ...
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... C8051T610/1/2/3/4/5/6/7 26.4. Watchdog Timer Mode A programmable watchdog timer (WDT) function is available through the PCA Module 4. The WDT is used to generate a reset if the time between writes to the WDT update register (PCA0CPH4) exceed a specified limit. The WDT can be configured and enabled/disabled as needed by software. With the WDTE bit set in the PCA0MD register, Module 4 operates as a watchdog timer (WDT). The Mod- ule 4 high byte is compared to the PCA counter high byte ...