PIC18F6525-I/PT Microchip Technology, PIC18F6525-I/PT Datasheet
PIC18F6525-I/PT
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PIC18F6525-I/PT Summary of contents
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... PIC18F6525/6621/8525/8621 2005 Microchip Technology Inc. Data Sheet 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D DS39612B ...
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... PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... PIC18F8525 48K 24576 3840 PIC18F8621 64K 32768 3840 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 External Memory Interface (PIC18F8525/8621 Devices Only): • Address capability Mbytes • 16-bit interface Analog Features: • 10-bit 16-channel Analog-to-Digital Converter (A/D): - Auto-Acquisition - Conversion available during Sleep • ...
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... REF 13 RF4/AN9 14 RF3/AN8 15 RF2/AN7/C1OUT 16 Note 1: ECCP2/P2A are multiplexed with RC1 when CCP2MX is set, or RE7 when CCP2MX is not set. 2: RG5 is multiplexed with MCLR and is only available when the MCLR Resets are disabled. DS39612B-page PIC18F6525 PIC18F6621 RB0/INT0/FLT0 48 RB1/INT1 47 RB2/INT2 46 RB3/INT3 45 RB4/KBI0 44 RB5/KBI1/PGM 43 RB6/KBI2/PGC ...
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... Microcontroller mode; or with RB3 when CCP2MX is cleared in all other program memory modes. 2: P1B/P1C/P3B/P3C are multiplexed with RE6:RE3 when ECCPMX is set and with RH7:RH4 when ECCPMX is not set. 3: RG5 is multiplexed with MCLR and is only available when the MCLR Resets are disabled. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 PIC18F8525 PIC18F8621 ...
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... Appendix C: Conversion Considerations ........................................................................................................................................... 378 Appendix D: Migration From Mid-Range to Enhanced Devices......................................................................................................... 378 Appendix E: Migration From High-End to Enhanced Devices............................................................................................................ 379 Index .................................................................................................................................................................................................. 381 On-Line Support................................................................................................................................................................................. 391 Systems Information and Upgrade Hot Line ...................................................................................................................................... 391 Reader Response .............................................................................................................................................................................. 392 PIC18F6525/6621/8525/8621 Product Identification System ............................................................................................................ 393 DS39612B-page 4 2005 Microchip Technology Inc. ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter- ature number) you are using. Customer Notification System Register on our Web site at www.microchip.com/cn to receive the most current information on all of our products. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 DS39612B-page 5 ...
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... PIC18F6525/6621/8525/8621 NOTES: DS39612B-page 6 2005 Microchip Technology Inc. ...
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... Kbytes or 64 Kbytes of code space. Other memory features are: • Data RAM and Data EEPROM: The PIC18F6525/ 6621/8525/8621 family also provides plenty of room for application data. The devices have 3840 bytes of data RAM, as well as 1024 bytes of data EEPROM for long term retention of nonvolatile data. • ...
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... I/O ports (7 on PIC18F6525/6621 devices PIC18F8525/8621 devices). 4. External program memory interface (present only on PIC18F8525/8621 devices) and 80-pin All other features for devices in the PIC18F6525/6621/ 8525/8621 family are identical. These are summarized in Table 1-1. for Block diagrams for PIC18F8525/8621 devices are provided in Figure 1-1 and Figure 1-2, respectively ...
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... FIGURE 1-1: PIC18F6525/6621 BLOCK DIAGRAM Table Pointer<21> inc/dec logic 20 PCLATU PCU Program Counter Address Latch Program Memory 31 Level Stack (48/64 Kbytes) Data Latch Table Latch 8 16 ROM Latch Instruction Decode and Control Power-up OSC2/CLKO Timer OSC1/CLKI Timing Oscillator Generation Start-up Timer ...
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... PIC18F6525/6621/8525/8621 FIGURE 1-2: PIC18F8525/8621 BLOCK DIAGRAM Table Pointer<21> 21 inc/dec logic 21 20 PCLATU PCU Program Counter Address Latch Program Memory 31 Level Stack (48/64 Kbytes) Data Latch Table Latch 8 16 ROM Latch (4) AD15:AD0, A19:16 Instruction Decode and Control Power-up OSC2/CLKO Timer OSC1/CLKI Timing ...
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... TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS Pin Number Pin Name PIC18F6X2X (9) MCLR/V /RG5 7 PP MCLR V PP RG5 OSC1/CLKI 39 OSC1 CLKI OSC2/CLKO/RA6 40 OSC2 CLKO RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX (CONFIG3H<0>) is not set (all Program Memory modes except Microcontroller) ...
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... PIC18F6525/6621/8525/8621 TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X2X RA0/AN0 24 RA0 AN0 RA1/AN1 23 RA1 AN1 RA2/AN2 REF RA2 AN2 V - REF RA3/AN3 REF RA3 AN3 V + REF RA4/T0CKI 28 RA4 T0CKI RA5/AN4/LVDIN 27 RA5 AN4 LVDIN RA6 Legend: TTL = TTL compatible input ...
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... TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X2X RB0/INT0/FLT0 48 RB0 INT0 FLT0 RB1/INT1 47 RB1 INT1 RB2/INT2 46 RB2 INT2 RB3/INT3/ECCP2/P2A 45 RB3 INT3 (1) ECCP2 (1) P2A RB4/KBI0 44 RB4 KBI0 RB5/KBI1/PGM 43 RB5 KBI1 PGM RB6/KBI2/PGC 42 RB6 KBI2 PGC RB7/KBI3/PGD 37 RB7 KBI3 ...
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... PIC18F6525/6621/8525/8621 TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X2X RC0/T1OSO/T13CKI 30 RC0 T1OSO T13CKI RC1/T1OSI/ECCP2/P2A 29 RC1 T1OSI (2) ECCP2 (2) P2A RC2/ECCP1/P1A 33 RC2 ECCP1 P1A RC3/SCK/SCL 34 RC3 SCK SCL RC4/SDI/SDA 35 RC4 SDI SDA RC5/SDO 36 RC5 SDO RC6/TX1/CK1 31 RC6 TX1 CK1 ...
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... TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X2X RD0/AD0/PSP0 58 RD0 (3) AD0 PSP0 RD1/AD1/PSP1 55 RD1 (3) AD1 PSP1 RD2/AD2/PSP2 54 RD2 (3) AD2 PSP2 RD3/AD3/PSP3 53 RD3 (3) AD3 PSP3 RD4/AD4/PSP4 52 RD4 (3) AD4 PSP4 RD5/AD5/PSP5 51 RD5 (3) AD5 PSP5 RD6/AD6/PSP6 50 RD6 (3) AD6 PSP6 RD7/AD7/PSP7 ...
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... PIC18F6525/6621/8525/8621 TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X2X RE0/AD8/RD/P2D 2 RE0 (3) AD8 RD P2D RE1/AD9/WR/P2C 1 RE1 (3) AD9 WR P2C RE2/AD10/CS/P2B 64 RE2 (3) AD10 CS P2B RE3/AD11/P3C 63 RE3 (3) AD11 (4) P3C RE4/AD12/P3B 62 RE4 (3) AD12 (4) P3B RE5/AD13/P1C 61 RE5 (3) AD13 (4) P1C RE6/AD14/P1B 60 RE6 (3) AD14 (4) P1B ...
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... TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X2X RF0/AN5 18 RF0 AN5 RF1/AN6/C2OUT 17 RF1 AN6 C2OUT RF2/AN7/C1OUT 16 RF2 AN7 C1OUT RF3/AN8 15 RF1 AN8 RF4/AN9 14 RF1 AN9 RF5/AN10/CV 13 REF RF1 AN10 CV REF RF6/AN11 12 RF6 AN11 RF7/SS 11 RF7 SS Legend: TTL = TTL compatible input ...
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... PIC18F6525/6621/8525/8621 TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X2X RG0/ECCP3/P3A 3 RG0 ECCP3 P3A RG1/TX2/CK2 4 RG1 TX2 CK2 RG2/RX2/DT2 5 RG2 RX2 DT2 RG3/CCP4/P3D 6 RG3 CCP4 P3D RG4/CCP5/P1D 8 RG4 CCP5 P1D RG5 7 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels ...
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... TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X2X RH0/A16 — RH0 A16 RH1/A17 — RH1 A17 RH2/A18 — RH2 A18 RH3/A19 — RH3 A19 RH4/AN12/P3C — RH4 AN12 (7) P3C RH5/AN13/P3B — RH5 AN13 (7) P3B RH6/AN14/P1C — RH6 ...
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... PIC18F6525/6621/8525/8621 TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X2X RJ0/ALE — RJ0 ALE RJ1/OE — RJ1 OE RJ2/WRL — RJ2 WRL RJ3/WRH — RJ3 WRH RJ4/BA0 — RJ4 BA0 RJ5/CE — RJ5 CE RJ6/LB — RJ6 LB RJ7/UB — RJ7 ...
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... OSCILLATOR CONFIGURATIONS 2.1 Oscillator Types The PIC18F6525/6621/8525/8621 devices can be operated in twelve different oscillator modes. The user can program four configuration bits (FOSC3, FOSC2, FOSC1 and FOSC0) to select one of these eight modes Low-Power Crystal 2. XT Crystal/Resonator 3. HS High-Speed Crystal/Resonator 4. RC External Resistor/Capacitor 5 ...
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... PIC18F6525/6621/8525/8621 TABLE 2-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Ranges Tested: Mode Freq C1 LP 32.0 kHz 200 kHz 47-68 pF 1.0 MHz 15 pF 4.0 MHz 4.0 MHz 15 pF 8.0 MHz 15-33 pF 20.0 MHz 15-33 pF 25.0 MHz 15-33 pF These values are for design guidance only. ...
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... OSC1. There are two types of PLL modes: Software Controlled PLL and Configuration Bits Controlled PLL. In Software Controlled PLL mode, PIC18F6525/6621/ 8525/8621 executes at regular clock frequency after all Reset conditions. During execution, the application can enable PLL and switch to 4x clock frequency operation by setting the PLLEN bit in the OSCCON register ...
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... The PIC18F6525/6621/8525/8621 devices include a feature that allows the system clock source to be switched from the main oscillator to an alternate low frequency clock source. For the PIC18F6525/6621/ 8525/8621 devices, this alternate clock source is the Timer1 oscillator low-frequency crystal (32 kHz, for example) has been attached to the Timer1 oscillator pins and the Timer1 oscillator has been enabled, the device can switch to a low-power execution mode ...
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... The setting of SCS0 = 1 supersedes SCS1 = 1. Legend Readable bit -n = Value at POR 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 Note: The Timer1 oscillator must be enabled and operating to switch the system clock source. The Timer1 oscillator is enabled by setting the T1OSCEN bit in the Timer1 Control register (T1CON) ...
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... PIC18F6525/6621/8525/8621 2.6.2 OSCILLATOR TRANSITIONS PIC18F6525/6621/8525/8621 devices contain circuitry to prevent “glitches” when switching between oscillator sources. Essentially, the circuitry waits for eight rising edges of the clock source that the processor is switch- ing to. This ensures that the new clock source is stable and that its pulse width will not be less than the shortest pulse width of the two clock sources ...
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... EC with PLL active, is shown in Figure 2-11. FIGURE 2-11: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (EC WITH PLL ACTIVE, SCS1 = T1OSI OSC1 PLL Clock Input Internal System Clock SCS (OSCCON<0>) Program Counter PC 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 ) plus an OST PLL T OSC T SCS ...
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... PIC18F6525/6621/8525/8621 If the main oscillator is configured in the RC, RCIO ECIO modes, there is no oscillator start-up time-out. Operation will resume after eight cycles of the main oscillator have been counted. A timing diagram, indi- cating the transition from the Timer1 oscillator to the main oscillator for RC, RCIO, EC and ECIO modes, is shown in Figure 2-12 ...
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... RESET The PIC18F6525/6621/8525/8621 devices differentiate between various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during Sleep d) Watchdog Timer (WDT) Reset (during normal operation) e) Programmable Brown-out Reset (BOR) f) RESET Instruction g) Stack Full Reset h) Stack Underflow Reset Most registers are unaffected by a Reset ...
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... MCLR is kept low long enough. Bringing MCLR high will begin execution immediately (Figure 3-5). This is useful for testing purposes or to synchronize more than one PIC18F6525/6621/8525/ 8621 device operating in parallel. Table 3-2 shows the Reset conditions for some Special Function Registers, while Table 3-3 shows the Reset conditions for all of the registers ...
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... Brown-out Reset Interrupt Wake-up from Sleep Legend unchanged unknown Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (0008h or 0018h). 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 (2) Power-up PWRTE = 1 ( 1024 ...
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... PIC18F6525/6621/8525/8621 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS Register Applicable Devices TOSU PIC18F6X2X PIC18F8X2X TOSH PIC18F6X2X PIC18F8X2X TOSL PIC18F6X2X PIC18F8X2X STKPTR PIC18F6X2X PIC18F8X2X PCLATU PIC18F6X2X PIC18F8X2X PCLATH PIC18F6X2X PIC18F8X2X PCL PIC18F6X2X PIC18F8X2X TBLPTRU PIC18F6X2X PIC18F8X2X TBLPTRH PIC18F6X2X PIC18F8X2X TBLPTRL PIC18F6X2X PIC18F8X2X ...
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... If MCLR function is disabled, PORTG<5> read-only bit. 8: Enabled only in Microcontroller mode for PIC18F8525/8621 devices. 9: The MEMCON register is unimplemented and reads all ‘0’s when the device is in Microcontroller mode. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 MCLR Resets Power-on Reset, WDT Reset Brown-out Reset RESET Instruction ...
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... PIC18F6525/6621/8525/8621 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices ADCON0 PIC18F6X2X PIC18F8X2X ADCON1 PIC18F6X2X PIC18F8X2X ADCON2 PIC18F6X2X PIC18F8X2X CCPR1H PIC18F6X2X PIC18F8X2X CCPR1L PIC18F6X2X PIC18F8X2X CCP1CON PIC18F6X2X PIC18F8X2X CCPR2H PIC18F6X2X PIC18F8X2X CCPR2L PIC18F6X2X PIC18F8X2X CCP2CON PIC18F6X2X PIC18F8X2X CCPR3H PIC18F6X2X PIC18F8X2X ...
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... If MCLR function is disabled, PORTG<5> read-only bit. 8: Enabled only in Microcontroller mode for PIC18F8525/8621 devices. 9: The MEMCON register is unimplemented and reads all ‘0’s when the device is in Microcontroller mode. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 MCLR Resets Power-on Reset, WDT Reset Brown-out Reset RESET Instruction ...
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... PIC18F6525/6621/8525/8621 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices (7) PORTG PIC18F6X2X PIC18F8X2X PORTF PIC18F6X2X PIC18F8X2X PORTE PIC18F6X2X PIC18F8X2X PORTD PIC18F6X2X PIC18F8X2X PORTC PIC18F6X2X PIC18F8X2X PORTB PIC18F6X2X PIC18F8X2X (5,6) PORTA PIC18F6X2X PIC18F8X2X SPBRGH1 PIC18F6X2X PIC18F8X2X BAUDCON1 PIC18F6X2X PIC18F8X2X SPBRGH2 ...
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... INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 3-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 T PWRT T OST T PWRT T T PWRT T VIA 1 kΩ RESISTOR CASE 1 ...
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... PIC18F6525/6621/8525/8621 FIGURE 3-6: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 3-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. ...
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... MEMORY ORGANIZATION There are three memory blocks in PIC18F6525/6621/ 8525/8621 devices. They are: • Program Memory • Data RAM • Data EEPROM Data and program memory use separate busses which allow for concurrent access of these blocks. Additional detailed information for Flash program memory and data EEPROM is provided in Section 5.0 “ ...
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... PIC18F6525/6621/8525/8621 FIGURE 4-1: INTERNAL PROGRAM MEMORY MAP AND STACK FOR PIC18FX525 PC<20:0> 21 CALL,RCALL,RETURN RETFIE,RETLW Stack Level 1 • • • Stack Level 31 000000h Reset Vector High Priority Interrupt Vector 000008h Low Priority Interrupt Vector 000018h On-Chip Flash Program Memory 00BFFFh 00C000h Read ‘0’ ...
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... Microcontroller mode 10 = Microprocessor mode 01 = Microcontroller with Boot Block mode 00 = Extended Microcontroller mode Note 1: This mode is available only on PIC18F8525/8621 devices. Legend Readable bit -n = Value after erase FIGURE 4-3: MEMORY MAPS FOR PIC18F6525/6621/8525/8621 PROGRAM MEMORY MODES Microprocessor (3) Mode 000000h 000000h On-Chip Program Memory ...
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... PIC18F6525/6621/8525/8621 4.2 Return Address Stack The return address stack allows any combination program calls and interrupts to occur. The PC (Program Counter) is pushed onto the stack when a CALL or RCALL instruction is executed interrupt is Acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction. PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions ...
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... POP instruction. The POP instruction discards the current TOS by decrementing the Stack Pointer. The previous value pushed onto the stack then becomes the TOS value. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 R/C-0 U-0 R/W-0 R/W-0 (1) — ...
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... PIC18F6525/6621/8525/8621 4.3 Fast Register Stack A “fast interrupt return” option is available for interrupts. A fast register stack is provided for the STATUS, WREG and BSR registers and is only one in depth. The stack is not readable or writable and is loaded with the current value of the corresponding register when the processor vectors for an interrupt ...
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... Instruction 2: GOTO Instruction 3: MOVFF 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 A fetch cycle begins with the Program Counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the “Instruction Register” (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles ...
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... PIC18F6525/6621/8525/8621 4.7.1 TWO-WORD INSTRUCTIONS The PIC18F6525/6621/8525/8621 devices have four two-word instructions: MOVFF, CALL, GOTO and LFSR. The second word of these instructions has the 4 MSBs set to ‘1’s and is a special kind of NOP instruction. The lower 12 bits of the second word contain data to be used by the instruction ...
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... Figure 4-7 shows the data memory organization for the PIC18F6525/6621/8525/8621 devices. The data memory map is divided into 16 banks that contain 256 bytes each. The lower 4 bits of the Bank Select Register (BSR< ...
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... PIC18F6525/6621/8525/8621 FIGURE 4-7: DATA MEMORY MAP FOR PIC18F6525/6621/8525/8621 DEVICES BSR<3:0> 00h = 0000 Bank 0 FFh 00h = 0001 Bank 1 FFh 00h = 0010 Bank 2 FFh 00h = 0011 Bank 3 FFh = 0100 Bank 4 Bank 5 to Bank 13 00h = 1110 Bank 14 FFh 00h = 1111 Bank 15 FFh When ‘a’ ...
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... FSR1L FC1h FE0h BSR FC0h Note 1: Unimplemented registers are read as ‘0’. 2: This register is not available on PIC18F6525/6621 devices and reads as ‘0’. 3: This is not a physical register. 4: Enabled only in Microcontroller mode for PIC18F8525/8621 devices. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 Name Address ...
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... F42h (1) F61h F41h — (1) F60h F40h — Note 1: Unimplemented registers are read as ‘0’. 2: This register is not available on PIC18F6525/6621 devices and reads as ‘0’. 3: This is not a physical register. 4: Enabled only in Microcontroller mode for PIC18F8525/8621 devices. DS39612B-page 50 Name Address Name (1) (1) — ...
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... RA6 and associated bits are configured as a port pin in RCIO and ECIO Oscillator modes only and read ‘0’ in all other oscillator modes. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: These registers are unused on PIC18F6525/6621 devices and read as ‘0’. 4: RG5 is available only if MCLR function is disabled in configuration. 5: Enabled only in Microcontroller mode for ...
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... RA6 and associated bits are configured as a port pin in RCIO and ECIO Oscillator modes only and read ‘0’ in all other oscillator modes. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: These registers are unused on PIC18F6525/6621 devices and read as ‘0’. 4: RG5 is available only if MCLR function is disabled in configuration. 5: Enabled only in Microcontroller mode for ...
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... RA6 and associated bits are configured as a port pin in RCIO and ECIO Oscillator modes only and read ‘0’ in all other oscillator modes. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: These registers are unused on PIC18F6525/6621 devices and read as ‘0’. 4: RG5 is available only if MCLR function is disabled in configuration. 5: Enabled only in Microcontroller mode for ...
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... RA6 and associated bits are configured as a port pin in RCIO and ECIO Oscillator modes only and read ‘0’ in all other oscillator modes. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: These registers are unused on PIC18F6525/6621 devices and read as ‘0’. 4: RG5 is available only if MCLR function is disabled in configuration. 5: Enabled only in Microcontroller mode for ...
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... The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 3: The MOVFF instruction embeds the entire 12-bit address in the instruction. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 4.11 Bank Select Register (BSR) The need for a large general purpose memory space dictates a RAM banking scheme ...
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... PIC18F6525/6621/8525/8621 4.12 Indirect Addressing, INDF and FSR Registers Indirect addressing is a mode of addressing data mem- ory, where the data memory address in the instruction is not fixed. An FSR register is used as a pointer to the data memory location that read or written. Since this pointer is in RAM, the contents can be modified by the program ...
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... Executed Opcode BSR<3:0> Instruction Fetched Opcode FIGURE 4-10: INDIRECT ADDRESSING 11 Location Select Note 1: For register file map detail, see Table 4-2. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 0h RAM Address FFFh 12 File Address = Access of an Indirect Addressing Register File FSR Indirect Addressing ...
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... PIC18F6525/6621/8525/8621 4.13 STATUS Register The STATUS register, shown in Register 4-3, contains the arithmetic status of the ALU. As with any other SFR, it can be the operand for any instruction. If the STATUS register is the destination for an instruc- tion that affects the Z, DC bits, the results of the instruction are not written ...
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... A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend Readable bit -n = Value at POR 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 Note recommended that the POR bit be set after a Power-on Reset has been detected, so that subsequent Power-on Resets may be detected. U-0 ...
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... PIC18F6525/6621/8525/8621 NOTES: DS39612B-page 60 2005 Microchip Technology Inc. ...
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... TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 5.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
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... PIC18F6525/6621/8525/8621 FIGURE 5-2: TABLE WRITE OPERATION (1) Table Pointer TBLPTRU TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table pointer actually points to one of eight holding registers, the address of which is determined by TBLPTRL<2:0>. The process for physically writing data to the program memory array is discussed in Section 5.5 “Writing to Flash Program Memory”. ...
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... RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 Does not initiate an EEPROM read Legend Readable bit -n = Value at POR 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 U-0 R/W-0 R/W-x — FREE WRERR W = Writable bit U = Unimplemented bit, read as ‘ ...
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... PIC18F6525/6621/8525/8621 5.2.2 TABLAT – TABLE LATCH REGISTER The Table Latch (TABLAT 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 5.2.3 TBLPTR – TABLE POINTER REGISTER The Table Pointer register (TBLPTR) addresses a byte within the program memory ...
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... MOVFW TABLAT, W MOVWF WORD_ODD 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
Page 68
... PIC18F6525/6621/8525/8621 5.4 Erasing Flash Program Memory The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. When initiating an erase sequence from the micro- controller itself, a block of 64 bytes of program memory is erased ...
Page 69
... CFGS bit to access program memory; • set WREN to enable byte writes. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 the holding registers are written. At the end of updating 8 registers, the EECON1 register must be written to, to start the programming operation with a long write. ...
Page 70
... PIC18F6525/6621/8525/8621 EXAMPLE 5-3: WRITING TO FLASH PROGRAM MEMORY MOVLW D'64 MOVWF COUNTER MOVLW BUFFER_ADDR_HIGH MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L MOVLW CODE_ADDR_UPPER MOVWF TBLPTRU MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_BLOCK TBLRD*+ MOVF TABLAT, W MOVWF POSTINC0 DECFSZ COUNTER BRA READ_BLOCK ...
Page 71
... Shaded cells are not used during Flash/EEPROM access. Note 1: Bit 21 of the TBLPTRU allows access to device configuration bits. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 ; point to Flash program memory ; access Flash program memory ; enable write to memory ; disable interrupts ...
Page 72
... PIC18F6525/6621/8525/8621 NOTES: DS39612B-page 70 2005 Microchip Technology Inc. ...
Page 73
... EXTERNAL MEMORY INTERFACE Note: The external memory interface is not implemented on PIC18F6525/6621 (64-pin) devices. The external memory interface is a feature of the PIC18F8525/8621 devices that allows the controller to access external memory devices (such as Flash, EPROM, SRAM, etc.) as program or data memory. The physical implementation of the interface uses 27 pins. These pins are reserved for external address/ data bus functions ...
Page 74
... PIC18F6525/6621/8525/8621 If the device fetches or accesses external memory while EBDIS = 1, the pins will switch to external bus. If the EBDIS bit is set by a program executing from external memory, the action of setting the bit will be delayed until the program branches into the internal memory. At that time, the pins will change from external bus to I/O ports ...
Page 75
... WRL Note 1: This signal only applies to table writes. See Section 5.1 “Table Reads and Table Writes”. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 In Byte Select mode, JEDEC standard Flash memories will require BA0 for the byte address line and one I/O line, to select between Byte and Word mode ...
Page 76
... PIC18F6525/6621/8525/8621 6.2.2 16-BIT WORD WRITE MODE Figure 6-2 shows an example of 16-bit Word Write mode for PIC18F8525/8621 devices. This mode is used for word-wide memories which include some of the EPROM and Flash type memories. This mode allows opcode fetches and table reads from all forms of 16-bit memory and table writes to any type of word- wide external memories ...
Page 77
... Note 1: This signal only applies to table writes. See Section 5.1 “Table Reads and Table Writes”. 2: Demultiplexing is only required when multiple memory devices are accessed. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 Flash and SRAM devices use different control signal combinations to implement Byte Select mode. JEDEC standard Flash memories require that a controller I/O port pin be connected to the memory’ ...
Page 78
... PIC18F6525/6621/8525/8621 6.2.4 16-BIT MODE TIMING The presentation of control signals on the external memory bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure 6-4 through Figure 6-6. FIGURE 6-4: EXTERNAL MEMORY BUS TIMING FOR TBLRD (MICROPROCESSOR MODE Apparent Q ...
Page 79
... EXTERNAL MEMORY BUS TIMING FOR SLEEP (MICROPROCESSOR MODE 00h A<19:16> AD<15:0> 0003h 3AAAh CE ALE OE Memory Opcode Fetch Cycle SLEEP from 007554h Instruction INST(PC – 2) Execution 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 00h 0E55h 3AABh Opcode Fetch Sleep Mode, MOVLW 55h from 007556h SLEEP Bus Inactive DS39612B-page 77 ...
Page 80
... PIC18F6525/6621/8525/8621 NOTES: DS39612B-page 78 2005 Microchip Technology Inc. ...
Page 81
... Please refer to parameter D122 (Section 27.0 “Electrical Characteristics”) for exact limits. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 7.1 EEADR and EEADRH The address register pair can address maximum of 1024 bytes of data EEPROM. The two range ...
Page 82
... PIC18F6525/6621/8525/8621 REGISTER 7-1: EECON1 REGISTER (ADDRESS FA6h) R/W-x R/W-x EEPGD CFGS bit 7 bit 7 EEPGD: Flash Program/Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access Configuration or Calibration registers 0 = Access Flash program or data EEPROM memory bit 5 Unimplemented: Read as ‘ ...
Page 83
... INTCON, GIE BCF EECON1, WREN 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 control bit (EECON1<6>) and then set the RD control bit (EECON1<0>). The data is available for the very next instruction cycle; therefore, the EEDATA register can be read by the next instruction. EEDATA will hold this value until another read operation or until it is written to by the user (during a write operation) ...
Page 84
... PIC18F6525/6621/8525/8621 7.5 Write Verify Depending on the application, good programming practice may dictate that the value written to the mem- ory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. 7.6 Protection Against Spurious Write There are conditions when the user may not want to write to the data EEPROM memory ...
Page 85
... IPR2 — CMIP — PIR2 — CMIF — PIE2 — CMIE — Legend unknown unchanged, — = unimplemented, read as ‘ 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 Bit 4 Bit 3 Bit 2 Bit 1 INT0IE RBIE TMR0IF INT0IF — — — EE Addr Register High ---- --00 FREE WRERR ...
Page 86
... PIC18F6525/6621/8525/8621 NOTES: DS39612B-page 84 2005 Microchip Technology Inc. ...
Page 87
... HARDWARE MULTIPLIER 8.1 Introduction hardware multiplier is included in the ALU of the PIC18F6525/6621/8525/8621 devices. By making the multiply a hardware operation, it completes in a single instruction cycle. This is an unsigned multiply that gives a 16-bit result. The result is stored in the 16-bit product register pair (PRODH:PRODL). The multiplier does not affect any flags in the ALUSTA register ...
Page 88
... PIC18F6525/6621/8525/8621 Example 8-3 shows the sequence unsigned multiply. Equation 8-1 shows the algorithm that is used. The 32-bit result is stored in four registers, RES3:RES0. EQUATION 8- UNSIGNED MULTIPLICATION ALGORITHM • RES3:RES0 = ARG1H:ARG1L ARG2H:ARG2L • • = (ARG1H ARG2H • • (ARG1H ARG2L • • (ARG1L ARG2H • ...
Page 89
... INTERRUPTS The PIC18F6525/6621/8525/8621 devices have multi- ple interrupt sources and an interrupt priority feature that allows each interrupt source to be assigned a high or a low priority level. The high priority interrupt vector is at 000008h, while the low priority interrupt vector is at 000018h. High priority interrupt events will override any low priority interrupts that may be in progress ...
Page 90
... PIC18F6525/6621/8525/8621 FIGURE 9-1: INTERRUPT LOGIC Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit TMR1IF TMR1IE TMR1IP XXXXIF XXXXIE XXXXIP Additional Peripheral Interrupts High Priority Interrupt Generation Low Priority Interrupt Generation Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit ...
Page 91
... Legend Readable bit -n = Value at POR 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt ...
Page 92
... PIC18F6525/6621/8525/8621 REGISTER 9-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 RBPU INTEDG0 bit 7 bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge ...
Page 93
... Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 R/W-0 R/W-0 R/W-0 INT3IE ...
Page 94
... PIC18F6525/6621/8525/8621 9.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request Flag registers (PIR1, PIR2 and PIR3). REGISTER 9-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 ...
Page 95
... A TMR1 or TMR3 register compare match occurred (must be cleared in software TMR1 or TMR3 register compare match occurred PWM mode: Unused in this mode. Legend Readable bit -n = Value at POR 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 U-0 R/W-0 R/W-0 — EEIF BCLIF W = Writable bit U = Unimplemented bit, read as ‘0’ ...
Page 96
... PIC18F6525/6621/8525/8621 REGISTER 9-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 U-0 — bit 7 bit 7-6 Unimplemented: Read as ‘0’ bit 5 RC2IF: USART2 Receive Interrupt Flag bit 1 = The USART2 receive buffer, RCREGx, is full (cleared when RCREGx is read The USART2 receive buffer is empty bit 4 ...
Page 97
... Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend Readable bit -n = Value at POR 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 R/W-0 R/W-0 R/W-0 ADIE RC1IE TX1IE SSPIE W = Writable bit U = Unimplemented bit, read as ‘ ...
Page 98
... PIC18F6525/6621/8525/8621 REGISTER 9-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 U-0 R/W-0 — CMIE bit 7 bit 7 Unimplemented: Read as ‘0’ bit 6 CMIE: Comparator Interrupt Enable bit 1 = Enables the comparator interrupt 0 = Disables the comparator interrupt bit 5 Unimplemented: Read as ‘0’ bit 4 EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit ...
Page 99
... Disables the TMR4 to PR4 match interrupt bit 2-0 CCPxIE: CCPx Interrupt Enable bit (ECCP3, CCP4 and CCP5 Enables the CCPx interrupt 0 = Disables the CCPx interrupt Legend Readable bit -n = Value at POR 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 U-0 R/W-0 R/W-0 R/W-0 — RC2IE TX2IE TMR4IE W = Writable bit U = Unimplemented bit, read as ‘ ...
Page 100
... PIC18F6525/6621/8525/8621 9.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2 and IPR3). The operation of the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set ...
Page 101
... High priority 0 = Low priority bit 0 CCP2IP: ECCP2 Interrupt Priority bit 1 = High priority 0 = Low priority Legend Readable bit -n = Value at POR 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 U-0 R/W-1 R/W-1 — EEIP BCLIP W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘ ...
Page 102
... PIC18F6525/6621/8525/8621 REGISTER 9-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 U-0 — bit 7 bit 7-6 Unimplemented: Read as ‘0’ bit 5 RC2IP: USART2 Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TX2IP: USART2 Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 TMR4IP: TMR4 to PR4 Match Interrupt Priority bit ...
Page 103
... POR: Power-on Reset Status bit For details of bit operation, see Register 4-4. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 4-4. Legend Readable bit -n = Value at POR 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 U-0 U-0 R/W-1 R-1 — — Writable bit U = Unimplemented bit, read as ‘ ...
Page 104
... PIC18F6525/6621/8525/8621 9.6 INT0 Interrupt External interrupts on the RB0/INT0/FLT0, RB1/INT1, RB2/INT2 and RB3/INT3 pins are edge-triggered; either rising if the corresponding INTEDGx bit is set in the INTCON2 register, or falling if the INTEDGx bit is clear. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxF, is set. This interrupt can be disabled by clearing the corresponding enable bit, INTxE ...
Page 105
... I/O PORTS Depending on the device selected, there are either seven or nine I/O ports available on PIC18F6525/6621/ 8525/8621 devices. Some of their pins are multiplexed with one or more alternate functions from the other peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin ...
Page 106
... PIC18F6525/6621/8525/8621 FIGURE 10-2: BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS RD LATA Data Bus LATA or PORTA Q CK Data Latch TRISA Q CK Analog TRIS Latch Input Mode RD TRISA PORTA To A/D Converter and LVD Modules Note 1: I/O pins have protection diodes to V FIGURE 10-4: BLOCK DIAGRAM OF RA6 PIN (WHEN ENABLED AS I/O) ...
Page 107
... Shaded cells are not used by PORTA. Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator modes only and read ‘0’ in all other oscillator modes. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 Input/output or analog input. Input/output or analog input. Input/output, analog input or V REF ...
Page 108
... PIC18F6525/6621/8525/8621 10.2 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i ...
Page 109
... To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). 3: For PIC18F8525/8621 parts, the ECCP2 input/output is multiplexed with RB3 if the CCP2MX bit is enabled (= 0) in the Configuration register and the device is operating in Microprocessor, Microprocessor with Boot Block or Extended Microcontroller mode. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 V DD Weak P Pull-up ...
Page 110
... PIC18F6525/6621/8525/8621 TABLE 10-3: PORTB FUNCTIONS Name Bit# Buffer RB0/INT0/FLT0 bit 0 TTL/ST RB1/INT1 bit 1 TTL/ST RB2/INT2 bit 2 TTL/ST RB3/INT3/ bit 3 TTL/ST (3) (3) ECCP2 /P2A RB4/KBI0 bit 4 TTL RB5/KBI1/PGM bit 5 TTL/ST RB6/KBI2/PGC bit 6 TTL/ST RB7/KBI3/PGD bit 7 TTL/ST Legend: TTL = TTL input Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt ...
Page 111
... Note 1: I/O pins have diode protection Peripheral output enable is only active if peripheral select is active. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 The pin override value is not loaded into the TRIS register. This allows read-modify-write of the TRIS register without concern due to peripheral overrides. ...
Page 112
... Note 1: Valid when CCP2MX is set in all devices and in all operating modes (default). RE7 is the alternate assignment for ECCP2/P2A for all PIC18F6525/6621 devices and PIC18F8525/8621 devices in Microcontroller modes when CCP2MX is not set; RB3 is the alternate assignment for PIC18F8525/8621 devices in all other operating modes ...
Page 113
... Alternate method ; to clear output ; data latches MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISD ; Set RD<3:0> as inputs ; RD<5:4> as outputs ; RD<7:6> as inputs 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 FIGURE 10-9: RD LATD Data Bus D WR LATD or PORTD CK Data Latch D WR TRISD CK TRIS Latch ...
Page 114
... PIC18F6525/6621/8525/8621 FIGURE 10-10: PORTD BLOCK DIAGRAM IN SYSTEM BUS MODE RD PORTD RD LATD Data Bus WR LATD or PORTD WR TRISD RD TRISD Bus Enable System Bus Data/TRIS Out Control Drive Bus Instruction Register Instruction Read Note 1: I/O pins have protection diodes to V DS39612B-page 112 Port Data ...
Page 115
... WAIT1 Legend unknown unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD. Note 1: Enabled only in Microcontroller mode for PIC18F8525/8621 devices. 2: This register is unused on PIC18F6525/6621 devices and reads as ‘0’. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 Function (1) Input/output port pin, address/data bus bit 0 or Parallel Slave Port bit 0. ...
Page 116
... Parallel Slave Port when bit PSPMODE (PSPCON<4>) is set. Section 4.1.1 “PIC18F6525/6621/8525/8621 Program Memory Modes” for more information.) DS39612B-page 114 When the Parallel Slave Port is active, three PORTE pins (RE0/AD8/RD/P2D, RE1/AD9/WR/P2C and RE2/ AD10/CS/P2B) function as its control inputs. This ...
Page 117
... RD LATE Data Bus WR LATE or PORTE WR TRISE RD TRISE Bus Enable System Bus Data/TRIS Out Control Drive Bus Instruction Register Instruction Read Note 1: I/O pins have protection diodes to V 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 I/O pin TRIS Override Pin RE0 Schmitt RE1 ...
Page 118
... Input buffers are Schmitt Triggers when in I/O or CCP/ECCP modes and TTL buffers when in System Bus or PSP Control modes. 2: Valid for all PIC18F6525/6621 devices and PIC18F8525/8621 devices when ECCPMX is set. Alternate assignments for P1B/P1C/P3B/P3C are RH7, RH6, RH5 and RH4, respectively. 3: Valid for all PIC18F6525/6621 devices and PIC18F8525/8621 devices in Microcontroller mode when CCP2MX is not set. RC1 is the default assignment for ECCP2/P2A for all devices in Microcontroller mode when CCP2MX is set ...
Page 119
... PORTF Data Latch D WR TRISF CK TRIS Latch RD TRISF RD PORTF To A/D Converter Note 1: I/O pins have diode protection to V 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 EXAMPLE 10-6: CLRF PORTF CLRF LATF MOVLW 0x07 MOVWF CMCON MOVLW 0x0F MOVWF ADCON1 ; Set PORTF as digital I/O ...
Page 120
... PIC18F6525/6621/8525/8621 FIGURE 10-14: RF6:RF3 AND RF0 PINS BLOCK DIAGRAM RD LATF Data Bus LATF or WR PORTF CK Q Data Latch TRISF CK Q Analog Input TRIS Latch Mode RD TRISF PORTF To A/D Converter or Comparator Input Note 1: I/O pins have diode protection to V DS39612B-page 118 FIGURE 10-15: ...
Page 121
... C2INV CVRCON CVREN CVROE CVRR CVRSS Legend unknown unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by PORTF. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 Function Input/output port pin or analog input. Input/output port pin, analog input or Comparator 2 output. Input/output port pin, analog input or Comparator 1 output. ...
Page 122
... PIC18F6525/6621/8525/8621 10.7 PORTG, TRISG and LATG Registers PORTG is a 6-bit wide port with 5 bidirectional pins (RG0:RG4) and one optional input only pin (RG5). The corresponding data direction register is TRISG. Setting a TRISG bit (= 1) will make the corresponding PORTG pin an input (i.e., put the corresponding output driver in a high-impedance mode) ...
Page 123
... TRISG — — — Legend unknown unchanged, — = unimplemented, read as ‘0’ Note 1: RG5 is available as an input only when MCLR is disabled. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 Schmitt Trigger Latch Filter Low-Level MCLR Detect Input/output port pin, Enhanced Capture 3 input/Compare 3 output/ PWM 3 output or Enhanced PWM 3 output P3A ...
Page 124
... PIC18F6525/6621/8525/8621 10.8 PORTH, LATH and TRISH Registers Note: PORTH is available only on PIC18F8525/ 8621 devices. PORTH is an 8-bit wide, bidirectional I/O port. The cor- responding data direction register is TRISH. Setting a TRISH bit (= 1) will make the corresponding PORTH pin an input (i.e., put the corresponding output driver in a high-impedance mode) ...
Page 125
... RD PORTH RD LATH Data Bus WR LATH or PORTH WR TRISH RD TRISH External Enable System Bus Address Out Control Drive System To Instruction Register Instruction Read Note 1: I/O pins have diode protection to V 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 Port Data 1 CK Data Latch TRIS Latch and V ...
Page 126
... Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in System Bus or Parallel Slave Port mode. 2: Valid only for PIC18F8525/8621 devices when ECCPMX is not set. The alternate assignments for P1B/P1C/P3B/P3C in all PIC18F6525/6621 devices and in PIC18F8525/8621 devices when ECCPMX is set are RE6, RE5, RE4 and RE3, respectively. TABLE 10-16: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH Name ...
Page 127
... On a Power-on Reset, these pins are configured as digital inputs. The pin override value is not loaded into the TRIS reg- ister. This allows read-modify-write of the TRIS register without concern due to peripheral overrides. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 EXAMPLE 10-9: CLRF PORTJ ; Initialize PORTG by ; clearing output ...
Page 128
... PIC18F6525/6621/8525/8621 FIGURE 10-22: RJ4:RJ0 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE RD PORTJ RD LATJ Data Bus WR LATJ or PORTJ WR TRISJ RD TRISJ Control Out System Bus External Enable Control Drive System Note 1: I/O pins have diode protection to V FIGURE 10-23: RJ7:RJ6 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE ...
Page 129
... LATJ Data Output Register TRISJ Data Direction Control Register for PORTJ Legend unknown unchanged 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 Function Input/output port pin or address latch enable control for external memory interface. Input/output port pin or output enable control for external memory interface ...
Page 130
... PIC18F6525/6621/8525/8621 10.10 Parallel Slave Port PORTD also operates as an 8-bit wide Parallel Slave Port, or microprocessor port, when control bit PSPMODE (PSPCON<4>) is set asynchronously readable and writable by the external world through RD control input pin, RE0/RD and WR control input pin, RE1/WR. Note: For PIC18F8525/8621 devices, the Parallel ...
Page 131
... Value at POR FIGURE 10-25: PARALLEL SLAVE PORT WRITE WAVEFORMS PORTD<7:0> IBF OBF PSPIF 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 R-0 R/W-0 R/W-0 U-0 IBOV PSPMODE — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Q3 ...
Page 132
... PIC18F6525/6621/8525/8621 FIGURE 10-26: PARALLEL SLAVE PORT READ WAVEFORMS PORTD<7:0> IBF OBF PSPIF TABLE 10-19: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Name Bit 7 Bit 6 Bit 5 PORTD Port Data Latch when written; Port pins when read LATD LATD Data Output bits TRISD PORTD Data Direction bits ...
Page 133
... Prescale value Legend Readable bit -n = Value at POR 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 Figure 11-1 shows a simplified block diagram of the Timer0 module in 8-bit mode and Figure 11-2 shows a simplified block diagram of the Timer0 module in 16-bit mode. The T0CON register (Register 11- readable and writable register that controls all the aspects of Timer0, including the prescale selection ...
Page 134
... PIC18F6525/6621/8525/8621 FIGURE 11-1: TIMER0 BLOCK DIAGRAM IN 8-BIT MODE OSC 1 T0CKI pin T0SE T0CS Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. FIGURE 11-2: TIMER0 BLOCK DIAGRAM IN 16-BIT MODE OSC 1 Programmable T0CKI pin Prescaler T0SE T0PS2, T0PS1, T0PS0 ...
Page 135
... Legend unknown unchanged, — = unimplemented locations, read as ‘0’. Shaded cells are not used by Timer0. Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator modes only and read ‘0’ in all other oscillator modes. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 11.2.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control, (i.e., it can be changed “ ...
Page 136
... PIC18F6525/6621/8525/8621 NOTES: DS39612B-page 134 2005 Microchip Technology Inc. ...
Page 137
... Stops Timer1 Legend Readable bit -n = Value at POR 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 Register 12-1 details the Timer1 Control register. This register controls the operating mode of the Timer1 module and contains the Timer1 oscillator enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit, TMR1ON (T1CON< ...
Page 138
... PIC18F6525/6621/8525/8621 12.1 Timer1 Operation Timer1 can operate in one of these modes: • timer • synchronous counter • asynchronous counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). When TMR1CS = 0, Timer1 increments every instruc- tion cycle. When TMR1CS = 1, Timer1 increments on every rising edge of the external clock input or the Timer1 oscillator, if enabled ...
Page 139
... Capacitor values are for design guidance only. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 12.3 Timer1 Interrupt The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit, TMR1IF (PIR1< ...
Page 140
... PIC18F6525/6621/8525/8621 12.6 Using Timer1 as a Real-Time Clock Adding an external LP oscillator to Timer1 (such as the one described in Section 12.2 “Timer1 Oscillator”) gives users the option to include RTC functionality to their applications. This is accomplished with an inexpensive watch crystal to provide an accurate time base and several lines of application code to calculate the time ...
Page 141
... T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu Legend unknown unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. Note 1: Enabled only in Microcontroller mode for PIC18F8525/8621 devices. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 Bit 4 Bit 3 Bit 2 Bit 1 INT0IE ...
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... PIC18F6525/6621/8525/8621 NOTES: DS39612B-page 140 2005 Microchip Technology Inc. ...
Page 143
... Prescaler Prescaler is 16 Legend Readable bit -n = Value at POR 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 13.1 Timer2 Operation Timer2 can be used as the PWM time base for the PWM mode of the ECCP module. The TMR2 register is readable and writable and is cleared on any device Reset ...
Page 144
... PIC18F6525/6621/8525/8621 13.2 Timer2 Interrupt The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon Reset. FIGURE 13-1: ...
Page 145
... Stops Timer3 Legend Readable bit -n = Value at POR 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 Figure 14 simplified block diagram of the Timer3 module. Register 14-1 shows the Timer3 Control register. This register controls the operating mode of the Timer3 module and sets the CCP/ECCP clock source. ...
Page 146
... PIC18F6525/6621/8525/8621 14.1 Timer3 Operation Timer3 can operate in one of these modes: • timer • synchronous counter • asynchronous counter The operating mode is determined by the clock select bit, TMR3CS (T3CON<1>). FIGURE 14-1: TIMER3 BLOCK DIAGRAM TMR3IF Overflow Interrupt Flag bit TMR3H T1OSC T1OSO/ ...
Page 147
... T3CCP2 T3CKPS1 T3CKPS0 Legend unknown unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 14.4 Resetting Timer3 Using an ECCP Special Trigger Output If either the ECCP1 or ECCP2 module is configured in Compare mode to generate a special event trigger (CCP1M3:CCP1M0 = 1011), this signal will reset Timer3 ...
Page 148
... PIC18F6525/6621/8525/8621 NOTES: DS39612B-page 146 2005 Microchip Technology Inc. ...
Page 149
... Prescaler Prescaler is 16 Legend Readable bit -n = Value at POR 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 15.1 Timer4 Operation Timer4 can be used as the PWM time base for the PWM mode of the CCP module. The TMR4 register is readable and writable and is cleared on any device Reset ...
Page 150
... PIC18F6525/6621/8525/8621 15.2 Timer4 Interrupt The Timer4 module has an 8-bit period register, PR4, which is both readable and writable. Timer4 increments from 00h until it matches PR4 and then resets to 00h on the next increment cycle. The PR4 register is initialized to FFh upon Reset. FIGURE 15-1: ...
Page 151
... CAPTURE/COMPARE/PWM (CCP) MODULES PIC18F6525/6621/8525/8621 devices all have a total of five CCP (Capture/Compare/PWM) modules. Two of these (CCP4 and CCP5) implement standard Capture, Compare and Pulse-Width Modulation (PWM) modes and are discussed in this section. The other three modules (ECCP1, ECCP2, ECCP3) standard Capture and Compare modes, as well as Enhanced PWM modes. These are discussed in Section 17.0 “ ...
Page 152
... PIC18F6525/6621/8525/8621 16.1 CCP Module Configuration Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a data register (CCPRx). The data register in turn is com- prised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte). All registers are both readable and writable. ...
Page 153
... RG3/CCP4/P1D pin and Edge Detect CCP1CON<3:0> Q’s 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 16.2.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit CCP4IE (PIE3<1>) clear to avoid false interrupts and should clear the flag bit, CCP4IF, following any such change in operating mode ...
Page 154
... PIC18F6525/6621/8525/8621 16.3 Compare Mode In Compare mode, the 16-bit CCPR1 register value is constantly compared against either the TMR1 or TMR3 register pair value. When a match occurs, the CCP4 pin can be: • driven high • driven low • toggled (high-to-low or low-to-high) • remain unchanged (that is, reflects the state of the ...
Page 155
... DC5B1 Legend unknown unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by Capture and Compare, Timer1 or Timer3. Note 1: Enabled only in Microcontroller mode for PIC18F8525/8621 devices. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 Bit 4 Bit 3 Bit 2 Bit 1 INT0IE RBIE TMR0IF ...
Page 156
... PIC18F6525/6621/8525/8621 16.4 PWM Mode In Pulse-Width Modulation (PWM) mode, the CCP4 pin produces 10-bit resolution PWM output. Since the CCP4 pin is multiplexed with the PORTG data latch, the TRISG<3> bit must be cleared to make the CCP4 pin an output. Note: Clearing the CCP4CON register will force the CCP4 PWM output latch to the default low level ...
Page 157
... Timer Prescaler (1, 4, 16) PR2 Value FFh Maximum Resolution (bits) 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 16.4.3 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 1. Select TMR2 or TMR4 by setting or clearing the ...
Page 158
... PIC18F6525/6621/8525/8621 TABLE 16-4: REGISTERS ASSOCIATED WITH PWM, TIMER2 AND TIMER4 Name Bit 7 Bit 6 Bit 5 INTCON GIE/GIEH PEIE/GIEL TMR0IE RCON IPEN — — (1) PIR1 PSPIF ADIF RC1IF (1) PIE1 PSPIE ADIE RC1IE (1) IPR1 PSPIP ADIP RC1IP PIR2 — CMIF — PIE2 — CMIE — ...
Page 159
... Note 1: Implemented only for ECCP1 and ECCP2; same as ‘1010’ for ECCP3. Legend Readable bit -n = Value at POR 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 Capture and Compare functions of the ECCP module are the same as the standard CCP module. The prototype control register for the Enhanced CCP module is shown in Register 17-1. In addition to the ...
Page 160
... ECCP MODULE OUTPUTS AND PROGRAM MEMORY MODES For PIC18F8525/8621 devices, the Program Memory mode of the device (Section 4.1.1 “PIC18F6525/6621/ 8525/8621 Program Memory Modes”) impacts both pin multiplexing and the operation of the module. The ECCP2 input/output (ECCP2/P2A) can be multi- plexed to one of three pins. By default, this is RC1 for all devices ...
Page 161
... P2A RE7 RC1/T1OS1 ECCP2 RC1/T1OS1 P2A RC1/T1OS1 P2A RC1/T1OS1 RE7/AD15 P2A RC1/T1OS1 RE7/AD15 P2A RC1/T1OS1 RE7/AD15 RG0 RE4 RE3 All PIC18F6525/6621 devices: RE4 RE3 P3A P3B RE3 P3A P3B P3C RE4/AD12 RE3/AD11 P3A P3B RE3/AD11 P3A P3B P3C RE6/AD14 RE5/AD13 P3A ...
Page 162
... PIC18F6525/6621/8525/8621 17.1.3 ECCP MODULES AND TIMER RESOURCES Like the standard CCP modules, the ECCP modules can utilize Timers depending on the mode selected. Timer1 and Timer3 are available for modules in Capture or Compare modes, while Timer2 and Timer4 are available for modules in PWM mode. ...
Page 163
... In PWM mode, CCPR1H is a read-only register. TABLE 17-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2.44 kHz Timer Prescaler (1, 4, 16) PR2 Value FFh Maximum Resolution (bits) 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 P1M1<1:0> CCP1M<3:0> ECCP1/P1A P1B Output R Q Controller ...
Page 164
... PIC18F6525/6621/8525/8621 17.4.3 PWM OUTPUT CONFIGURATIONS The P1M1:P1M0 bits in the CCP1CON register allow one of four configurations: • Single Output • Half-Bridge Output • Full-Bridge Output, Forward mode • Full-Bridge Output, Reverse mode FIGURE 17-2: PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) SIGNAL CCP1CON <7:6> ...
Page 165
... Dead-Band Delay” for more details on dead-band delay operations. Since the P1A and P1B outputs are multiplexed with the PORTC<2> and PORTE<6> data latches, the TRISC<2> and TRISE<6> bits must be cleared to configure P1A and P1B as outputs. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 0 Duty Cycle Period (1) Delay ...
Page 166
... PIC18F6525/6621/8525/8621 FIGURE 17-5: EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS Standard Half-Bridge Circuit (“Push-Pull”) PIC18F6X2X/8X2X Half-Bridge Output Driving a Full-Bridge Circuit PIC18F6X2X/8X2X P1A P1B DS39612B-page 164 V+ FET Driver P1A Load FET Driver P1B V- V+ FET Driver Load FET Driver FET Driver FET Driver ...
Page 167
... Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active-high. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 P1A, P1B, P1C and P1D outputs are multiplexed with the PORTC<2>, PORTE<6:5> and PORTG<4> data latches. The TRISC<2>, TRISC<6:5> and TRISG<4> ...
Page 168
... PIC18F6525/6621/8525/8621 FIGURE 17-7: EXAMPLE OF FULL-BRIDGE APPLICATION PIC18F6X2X/8X2X P1A P1B P1C P1D 17.4.5.1 Direction Change in Full-Bridge Mode In the Full-Bridge Output mode, the P1M1 bit in the CCP1CON register allows users to control the forward/ reverse direction. When the application firmware changes this direction control bit, the module will assume the new direction on the next PWM cycle ...
Page 169
... Note 1: All signals are shown as active-high the turn-on delay of power switch QC and its driver the turn-off delay of power switch QD and its driver. OFF 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 (1) Period DC , depending on the Timer2 prescaler value. The modulated P1B and P1D signals OSC Forward Period t1 ...
Page 170
... PIC18F6525/6621/8525/8621 17.4.6 PROGRAMMABLE DEAD-BAND DELAY In half-bridge applications where all power switches are modulated at the PWM frequency at all times, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on ...
Page 171
... Drive Pins B and D to ‘0’ Drive Pins B and D to ‘1’ Pins B and D tri-state Legend Readable bit -n = Value at POR 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 R/W-0 R/W-0 R/W-0 R/W Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘ ...
Page 172
... PIC18F6525/6621/8525/8621 17.4.7.1 Auto-Shutdown and Automatic Restart The auto-shutdown feature can be configured to allow automatic restarts of the module following a shutdown event. This is enabled by setting the P1RSEN bit of the ECCP1DEL register (ECCP1DEL<7>). In Shutdown mode with PRSEN = 1 (Figure 17-10), the ECCPASE bit will remain set for as long as the cause of the shutdown continues ...
Page 173
... Set the ECCP1ASE bit (ECCP1AS<7>). • Configure the comparators using the CMCON register. • Configure the comparator inputs as analog inputs. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 8. If auto-restart operation is required, set the P1RSEN bit (ECCP1DEL<7>). 9. Configure and start TMR2: • Clear the TMR2 interrupt flag bit by clearing the TMR2IF bit (PIR1< ...
Page 174
... PIC18F6525/6621/8525/8621 TABLE 17-5: REGISTERS ASSOCIATED WITH ECCP MODULES AND TIMER1 TO TIMER4 Name Bit 7 Bit 6 Bit 5 INTCON GIE/GIEH PEIE/GIEL TMR0IE RCON IPEN — — (1) PIR1 PSPIF ADIF RC1IF (1) PIE1 PSPIE ADIE RC1IE (1) IPR1 PSPIP ADIP RC1IP PIR2 — CMIF — PIE2 — ...
Page 175
... MSSP 2 module is operated in SPI mode. Additional details are provided under the individual sections. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 18.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four modes of ...
Page 176
... PIC18F6525/6621/8525/8621 18.3.1 REGISTERS The MSSP module has four registers for SPI mode operation. These are: • MSSP Control Register 1 (SSPCON1) • MSSP Status Register (SSPSTAT) • Serial Receive/Transmit Buffer Register (SSPBUF) • MSSP Shift Register (SSPSR) – Not directly accessible SSPCON1 and SSPSTAT are the control and status registers in SPI mode operation ...
Page 177
... SPI Master mode, clock = F 0000 = SPI Master mode, clock = F Note: Bit combinations not specifically listed here are either reserved or implemented mode only. Legend Readable bit -n = Value at POR 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 /64 OSC /16 OSC ...
Page 178
... PIC18F6525/6621/8525/8621 18.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1<5:0>) and SSPSTAT<7:6>. These control bits allow the following to be specified: • Master mode (SCK is the clock output) • Slave mode (SCK is the clock input) • ...
Page 179
... Shift Register (SSPSR) LSb MSb PROCESSOR 1 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 18.3.4 TYPICAL CONNECTION Figure 18-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their programmed clock edge and latched on the opposite edge of the clock ...
Page 180
... PIC18F6525/6621/8525/8621 18.3.5 MASTER MODE The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 18- broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be dis- abled (programmed as an input) ...
Page 181
... Flag SSPSR to SSPBUF 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 must be high. When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven even if in the middle of a transmitted byte and becomes a floating output ...
Page 182
... PIC18F6525/6621/8525/8621 FIGURE 18-5: SPI™ MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 SDI (SMP = 0) bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF FIGURE 18-6: SPI™ MODE WAVEFORM (SLAVE MODE WITH CKE = 1) ...
Page 183
... Shaded cells are not used by the MSSP in SPI™ mode. Note 1: Enabled only in Microcontroller mode for PIC18F8525/8621 devices. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 18.3.10 BUS MODE COMPATIBILITY Table 18-1 shows the compatibility between the standard SPI modes and the states of the CKP and CKE control bits ...
Page 184
... PIC18F6525/6621/8525/8621 2 18 Mode 2 The MSSP module mode fully implements all master and slave functions (including general call support) and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master func- tion). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing ...
Page 185
... SSPBUF is empty In Receive mode SSPBUF is full (does not include the ACK and Stop bits SSPBUF is empty (does not include the ACK and Stop bits) Legend Readable bit -n = Value at POR 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 2 C MODE) R-0 R-0 R-0 D/A P ...
Page 186
... PIC18F6525/6621/8525/8621 REGISTER 18-4: SSPCON1: MSSP CONTROL REGISTER 1 (I R/W-0 R/W-0 WCOL SSPOV bit 7 bit 7 WCOL: Write Collision Detect bit In Master Transmit mode write to the SSPBUF register was attempted while the I a transmission to be started (must be cleared in software collision In Slave Transmit mode: ...
Page 187
... For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I this bit may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). Legend Readable bit -n = Value at POR 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 2 C MODE) R/W-0 R/W-0 R/W-0 ACKDT ...
Page 188
... PIC18F6525/6621/8525/8621 18.4.2 OPERATION The MSSP module functions are enabled by setting MSSP Enable bit, SSPEN (SSPCON<5>). The SSPCON1 register allows control of the I ation. Four mode selection bits (SSPCON<3:0>) allow 2 one of the following I C modes to be selected: 2 • Master mode, clock = (F /4) x (SSPADD + 1) ...
Page 189
... The clock must be released by setting bit CKP (SSPCON<4>). See Section 18.4.4 “Clock Stretching” for more detail. 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 18.4.3.3 Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set ...
Page 190
... PIC18F6525/6621/8525/8621 2 FIGURE 18-8: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) DS39612B-page 188 2005 Microchip Technology Inc. ...
Page 191
... FIGURE 18-9: I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 DS39612B-page 189 ...
Page 192
... PIC18F6525/6621/8525/8621 2 FIGURE 18-10: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) DS39612B-page 190 2005 Microchip Technology Inc. ...
Page 193
... FIGURE 18-11: I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 DS39612B-page 191 ...
Page 194
... PIC18F6525/6621/8525/8621 18.4.4 CLOCK STRETCHING Both 7-bit and 10-bit Slave modes implement automatic clock stretching during a transmit sequence. The SEN bit (SSPCON2<0>) allows clock stretching to be enabled during receives. Setting SEN will cause the SCL pin to be held low at the end of each data receive sequence ...
Page 195
... DX SCL CKP WR SSPCON 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other 2 devices on the I C bus have deasserted SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 18-12) ...
Page 196
... PIC18F6525/6621/8525/8621 2 FIGURE 18-13: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) DS39612B-page 194 2005 Microchip Technology Inc. ...
Page 197
... FIGURE 18-14: I C™ SLAVE MODE TIMING SEN = 1 (RECEPTION, 10-BIT ADDRESS) 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 DS39612B-page 195 ...
Page 198
... PIC18F6525/6621/8525/8621 18.4.5 GENERAL CALL ADDRESS SUPPORT 2 The addressing procedure for the I C bus is such that the first byte after the Start condition usually deter- mines which device will be the slave addressed by the master. The exception is the general call address which can address all devices. When this address is used, all ...
Page 199
... FIGURE 18-16: MSSP BLOCK DIAGRAM (I SDA SDA In SCL SCL In Bus Collision 2005 Microchip Technology Inc. PIC18F6525/6621/8525/8621 Note: The MSSP module, when configured Master mode, does not allow queueing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSPBUF register to initiate transmission before the Start condition is complete ...
Page 200
... PIC18F6525/6621/8525/8621 2 18.4.6 Master Mode Operation The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I not be released ...