PIC32MX440F512H-80I/PT Microchip Technology, PIC32MX440F512H-80I/PT Datasheet - Page 62

• Manufacturer Part Number: PIC32MX440F512H-80I/PT
• Description: IC PIC MCU FLASH 512K 64-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX440F512H-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 64-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 51
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC32MX
APPENDIX C:
Revision E (July 2009)
This version of the document contains the following
additions and updates:
• Minor changes to style and formatting have been
• Added the following devices to Table 5-1:
• Updated MCLR pulse line to show active-high
• Updated Step 7 of Table 11-1 to clarify repeat of
• The following instructions in Table 13-1 were
• Added the following devices to Table 17-1:
DS61145G-page 62
incorporated throughout the document
- PIC32MX565F256H
- PIC32MX575F512H
- PIC32MX675F512H
- PIC32MX795F512H
- PIC32MX575F512L
- PIC32MX675F512L
- PIC32MX795F512L
(P20) in Figure 7-1
the last instruction in the step
updated:
- Seventh, ninth and eleventh instructions in
- All instructions in Step 2
- First instruction in Step 3
- Third instruction in Step 4
- PIC32MX565F256H
- PIC32MX575F512H
- PIC32MX575F512L
- PIC32MX675F512H
- PIC32MX675F512L
- PIC32MX795F512H
- PIC32MX795F512L
Step 1
REVISION HISTORY
• Updated address values in Table 17-2
• Added the following devices to Table 17-5:
• Added Notes 1-3 and the following bits to the
• Updated the DEVID Summary (see Table 18-2)
• Updated ICESEL bit description and added the
• Updated DEVID: Device and Revision ID register
• Added Device IDs and Revision table (Table 18-5)
• Added MCLR High Time (parameter P20) to
• Added Appendix B: “Hex File Format” and
- PIC32MX565F256H
- PIC32MX575F512H
- PIC32MX675F512H
- PIC32MX795F512H
- PIC32MX575F512L
- PIC32MX675F512L
- PIC32MX795F512L
DEVCFG - Device Configuration Word Summary
and the DEVCFG3: Device Configuration Word 3
(see Table 18-1 and Register 18-4):
- FVBUSIO
- FUSBIDIO
- FCANIO
- FETHIO
- FMIIEN
- FPBDIV<1:0>
- FJTAGEN
FJTAGEN bit in DEVCFG0: Device Configuration
Word 0 (see Register 16-1)
(see Register 18-5)
Table 20-1
Appendix C: “Revision History”
© 2010 Microchip Technology Inc.