DSPIC30F4013-20I/PT Microchip Technology, DSPIC30F4013-20I/PT Datasheet - Page 7

• Manufacturer Part Number: DSPIC30F4013-20I/PT
• Description: IC DSPIC MCU/DSP 48K 44TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4013-20I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 30
• Flash Memory Size: 48KB
• Supply Voltage Range: 2.5V To 5.5V
• Package: 44TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 30
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 13-chx12-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC30F006 - MODULE SKT FOR DSPIC30F 44TQFPAC164305 - MODULE SKT FOR PM3 44TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F401320IPT

9. Module: Output Compare in PWM Mode
10. Module: Output Compare
11. Module: Special Function Registers
© 2008 Microchip Technology Inc.
If the desire duty cycle is ‘0’ (OCxRS = 0), the
module will generate a high level glitch of 1 T
The second problem is that on the next cycle after
the glitch, the OC pin does not go high, or in other
words, it misses the next compare for any value
written on OCxRS.
Work around
There are two possible solutions to this problem:
1. Load a value greater than ‘0’ to the OCxRS
2. If the application requires 0% duty cycles, the
A glitch will be produced on an output compare pin
under the following conditions:
• The user software initially drives the I/O pin
• The output compare module is configured and
When these events occur, the output compare
module will drive the pin low for one instruction
cycle (T
Work around
None. However, the user may use a timer interrupt
and write to the associated PORT register to
control the pin manually.
The I/O Port register values can be changed by
writing to the following address locations, which
are located in unimplemented memory space. A
write to these unimplemented addresses could
cause an I/O pin configured as an output to
change states. This state change could be
confirmed by reading either the PORT or LAT
register associated with the pin.
PORTB will be modified by a write to address 0x0C8
PORTC will be modified by a write to address 0x0CE
PORTD will be modified by a write to address 0x0D4
PORTE will be modified by a write to address 0x0DA
PORTF will be modified by a write to address 0x0E0
Work around
User software should avoid writing to the
unimplemented locations listed above.
high using the output compare module or a
write to the associated PORT register.
enabled to drive the pin low at some later time
(OCxCON = 0x0002 or OCxCON = 0x0003).
register when operating n PWM mode. In this
case, no 0% duty cycle is achievable.
output compare module can be disabled
for 0% duty cycles, and re-enabled for
non-zero percent duty cycles.
CY
) after the module is enabled.
CY
.
12. Module: 4x PLL Operation
13. Module: I
dsPIC30F3014/4013
When the 4x PLL mode of operation is selected,
the specified input frequency range of 4-10 MHz is
not fully supported.
When device V
frequency must be in the range of 4-5 MHz. When
device V
must be in the range of 4-6 MHz for both industrial
and extended temperature ranges.
Work around
1. Use 8x PLL or 16x PLL mode of operation and
2. Use the EC without PLL Clock mode with a
The SDA pin is the data pin for the I
This pin is multiplexed the RF2 pin. The state of
the LATF<2> overrides the SDA pin functionality
when LATF<2> is high. In order to use the I
module successfully, the LATF<2> bit must be low.
Work around
Before enabling the I
LATF<2> bit. The I
as long as this bit remains low.
set final device clock speed using the
POST<1:0> oscillator postscaler control bits
(OSCCON<7:6>).
suitable clock frequency to obtain the equivalent
4x PLL clock rate.
DD
is 3.0-3.6V, the 4x PLL input frequency
2
C
DD
2
C module will operate properly
is 2.5-3.0V, the 4x PLL input
2
C module, clear the
DS80228K-page 7
2
C module.
2
C