PIC18LF2550-I/SO Microchip Technology, PIC18LF2550-I/SO Datasheet - Page 304

• Manufacturer Part Number: PIC18LF2550-I/SO
• Description: IC PIC MCU FLASH 16KX16 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF2550-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Eeprom Size: 256 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI/I2C/EAUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163025, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Package: 28SOIC W
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F2455/2550/4455/4550
25.5
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PIC
The user program memory is divided into five blocks.
One of these is a boot block of 2 Kbytes. The remainder
of the memory is divided into four blocks on binary
boundaries.
FIGURE 25-5:
TABLE 25-3:
DS39632D-page 302
300008h
300009h
30000Ah
30000Bh
30000Ch
30000Dh
Legend: Shaded cells are unimplemented.
Note 1:
®
devices.
File Name
Program Verification and
Code Protection
(PIC18F2455/2555)
Unimplemented in PIC18FX455 devices; maintain this bit set.
Unimplemented
Unimplemented
CONFIG5L
CONFIG5H
CONFIG6L
CONFIG6H
CONFIG7L
CONFIG7H
24 Kbytes
Boot Block
Read ‘0’s
Read ‘0’s
Block 0
Block 1
Block 2
SUMMARY OF CODE PROTECTION REGISTERS
MEMORY SIZE/DEVICE
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2455/2550/4455/4550
WRTD
Bit 7
CPD
—
—
—
—
(PIC18F2550/4550)
Unimplemented
32 Kbytes
Boot Block
EBTRB
Read ‘0’s
WRTB
Bit 6
CPB
Block 0
Block 1
Block 2
Block 3
—
—
—
Preliminary
WRTC
Bit 5
—
—
—
—
—
000000h
0007FFh
000800h
001FFFh
002000h
003FFFh
004000h
005FFFh
006000h
007FFFh
008000h
1FFFFFh
Address
Range
Each of the five blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 25-5 shows the program memory organization
for 24 and 32-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 25-3.
Bit 4
—
—
—
—
—
—
EBTR3
WRT3
CP3
Bit 3
(Unimplemented Memory Space)
—
—
—
(1)
(1)
Block Code Protection
(1)
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
CP1, WRT1, EBTR1
CP2, WRT2, EBTR2
CP3, WRT3, EBTR3
Controlled By:
EBTR2
WRT2
Bit 2
CP2
© 2007 Microchip Technology Inc.
—
—
—
EBTR1
WRT1
Bit 1
CP1
—
—
—
EBTR0
WRT0
Bit 0
CP0
—
—
—