PIC18F2525-I/SO Microchip Technology, PIC18F2525-I/SO Datasheet - Page 216
![IC MCU FLASH 24KX16 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC18F2525-I/SO
Manufacturer Part Number
PIC18F2525-I/SO
Description
IC MCU FLASH 24KX16 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(46 pages)
2.PIC18F2525-ISO.pdf
(412 pages)
3.PIC18F2525-ISO.pdf
(18 pages)
4.PIC18F2525-ISO.pdf
(18 pages)
5.PIC18F2525-ISO.pdf
(6 pages)
6.PIC18F2525-ISO.pdf
(6 pages)
7.PIC18LF4620-IP.pdf
(390 pages)
Specifications of PIC18F2525-I/SO
Program Memory Type
FLASH
Program Memory Size
48KB (24K x 16)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3986 B
Interface Type
SPI, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
25
Number Of Timers
1 x 8
Operating Supply Voltage
4.2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163022, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Package
28SOIC W
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MILI3DB18F4620 - BOARD DAUGHTER ICEPIC3
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F2525-I/SO
Manufacturer:
HITTITE
Quantity:
101
- PIC18F2221-ISO PDF datasheet
- PIC18F2525-ISO PDF datasheet #2
- PIC18F2525-ISO PDF datasheet #3
- PIC18F2525-ISO PDF datasheet #4
- PIC18F2525-ISO PDF datasheet #5
- PIC18F2525-ISO PDF datasheet #6
- PIC18LF4620-IP PDF datasheet #7
- Current page: 216 of 412
- Download datasheet (7Mb)
PIC18F2525/2620/4525/4620
FIGURE 18-7:
TABLE 18-6:
18.2.4
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the Baud Rate Generator
is inactive and a proper byte reception cannot be per-
formed. The auto-wake-up feature allows the controller
to wake-up due to activity on the RX/DT line while the
EUSART is operating in Asynchronous mode.
The auto-wake-up feature is enabled by setting the
WUE bit (BAUDCON<1>). Once set, the typical receive
sequence on RX/DT is disabled and the EUSART
remains in an Idle state, monitoring for a wake-up event
independent of the CPU mode. A wake-up event
consists of a high-to-low transition on the RX/DT line.
(This coincides with the start of a Sync Break or a
Wake-up Signal character for the LIN protocol.)
DS39626E-page 214
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
BAUDCON
SPBRGH
SPBRG
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1:
Name
Note:
RX (pin)
Rcv Shift Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word causing
the OERR (overrun) bit to be set.
These bits are unimplemented on 28-pin devices and read as ‘0’.
AUTO-WAKE-UP ON SYNC
BREAK CHARACTER
EUSART Receive Register
GIE/GIEH PEIE/GIEL
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
ABDOVF
PSPIE
PSPIP
PSPIF
CSRC
SPEN
Bit 7
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
(1)
(1)
(1)
ASYNCHRONOUS RECEPTION
Start
bit
bit 0
RCIDL
ADIE
ADIP
Bit 6
ADIF
RX9
TX9
bit 1
TMR0IE
RXDTP
SREN
TXEN
RCIF
RCIE
RCIP
Bit 5
bit 7/8
TXCKP
Stop
INT0IE
CREN
SYNC
bit
Bit 4
TXIF
TXIE
TXIP
Word 1
RCREG
Start
bit
ADDEN
SENDB
bit 0
BRG16
Following a wake-up event, the module generates an
RCIF interrupt. The interrupt is generated synchro-
nously to the Q clocks in normal operating modes
(Figure 18-8) and asynchronously, if the device is in
Sleep mode (Figure 18-9). The interrupt condition is
cleared by reading the RCREG register.
The WUE bit is automatically cleared once a low-to-
high transition is observed on the RX line following the
wake-up event. At this point, the EUSART module is in
Idle mode and returns to normal operation. This signals
to the user that the Sync Break event is over.
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
TMR0IF
CCP1IE
CCP1IP
CCP1IF
bit 7/8
BRGH
FERR
Word 2
RCREG
Bit 2
—
Stop
bit
TMR2IE
TMR2IP
TMR2IF
INT0IF
OERR
TRMT
Start
© 2008 Microchip Technology Inc.
WUE
Bit 1
bit
TMR1IE
TMR1IP
TMR1IF
ABDEN
RX9D
TX9D
RBIF
bit 7/8
Bit 0
Stop
bit
on page
Values
Reset
49
52
52
52
51
51
51
51
51
51
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