PIC16F87-I/SS Microchip Technology, PIC16F87-I/SS Datasheet - Page 122

IC MCU FLASH 4KX14 EEPROM 20SSOP

PIC16F87-I/SS

Manufacturer Part Number
PIC16F87-I/SS
Description
IC MCU FLASH 4KX14 EEPROM 20SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr

Specifications of PIC16F87-I/SS

Program Memory Type
FLASH
Program Memory Size
7KB (4K x 14)
Package / Case
20-SSOP
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Eeprom Size
256 x 8
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
368 B
Interface Type
SSP/USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
16
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC164307 - MODULE SKT FOR PM3 28SSOP
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F87-I/SS
Manufacturer:
SEMELAB
Quantity:
77
PIC16F87/88
12.5
The A/D module can operate during SLEEP mode. This
requires that the A/D clock source be set to RC
(ADCS1:ADCS0 = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed, which eliminates all digital
switching noise from the conversion. When the conver-
sion is completed, the GO/DONE bit will be cleared and
the result loaded into the ADRES register. If the A/D
interrupt is enabled, the device will wake-up from
SLEEP. If the A/D interrupt is not enabled, the A/D mod-
ule will then be turned off, although the ADON bit will
remain set.
When the A/D clock source is another clock option (not
RC), a SLEEP instruction will cause the present conver-
sion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
Turning off the A/D places the A/D module in its lowest
current consumption state.
TABLE 12-2:
DS30487B-page 120
0Bh, 8Bh
10Bh, 18Bh
0Ch
8Ch
1Eh
9Eh
1Fh
9Fh
9Bh
05h
05h, 106h PORTB
85h
86h, 186h TRISB
Legend:
Note 1:
Address
Note:
2:
A/D Operation During SLEEP
PORTA
INTCON
PIR1
PIE1
ADRESH
ADRESL
ADCON0
ADCON1
ANSEL
(PIC16F87)
(PIC16F88)
(PIC16F87)
(PIC16F88)
TRISA
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
PIC16F88 only.
Pin 5 is an input only; the state of the TRISA5 bit has no effect and will always read ‘1’.
For the A/D module to operate in SLEEP,
the A/D clock source must be set to RC
(ADCS1:ADCS0 = 11). To perform an A/D
conversion in SLEEP, ensure the SLEEP
instruction
instruction that sets the GO/DONE bit.
Name
(1)
REGISTERS/BITS ASSOCIATED WITH A/D
(1)
(1)
(1)
(1)
TRISA7 TRISA6 TRISA5
TRISB7 TRISB6
ADCS1 ADCS0
A/D Result Register High Byte
A/D Result Register Low Byte
ADFM
Bit 7
RA7
RB7
GIE
immediately
ADCS2
ADIE
PEIE
ADIF
Bit 6
AN6
RA6
RB6
follows
TMR0IE
TRISB5 TRISB4 TRISB3
VCFG1
CHS2
RCIE
RCIF
Bit 5
AN5
RA5
RB5
(2)
PORTA Data Direction Register
VCFG0
the
CHS1
INTE
Preliminary
Bit 4
TXIF
TXIE
AN4
RA4
RB4
SSPIE
SSPIF
CHS0 GO/DONE
RBIE
Bit 3
AN3
RA3
RB3
12.6
A device RESET forces all registers to their RESET
state. The A/D module is disabled and any conversion
in progress is aborted. All A/D input pins are configured
as analog inputs.
The value that is in the ADRESH:ADRESL registers
is
ADRESH:ADRESL registers will contain unknown data
after a Power-on Reset.
12.7
An A/D conversion can be started by the “special event
trigger” of the CCP module. This requires that the
CCP1M3:CCP1M0 bits (CCP1CON<3:0>) be pro-
grammed as ‘1011’ and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the GO/
DONE bit will be set, starting the A/D conversion and
the Timer1 counter will be reset to zero. Timer1 is reset
to automatically repeat the A/D acquisition period with
minimal
ADRESH:ADRESL to the desired location). The appro-
priate analog input channel must be selected and the
minimum acquisition done before the “special event
trigger” sets the GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared), then
the “special event trigger” will be ignored by the A/D
module, but will still reset the Timer1 counter.
TMR0IF
CCP1IF
CCP1IE
TRISB2
not
Bit 2
AN2
RA2
RB2
Effects of a RESET
Use of the CCP Trigger
modified
software
TMR2IE TMR1IE -000 0000 -000 0000
TMR2IF TMR1IF
TRISB1 TRISB0
INTF
Bit 1
AN1
RA1
RB1
for
ADON
RBIF
Bit 0
AN0
RA0
RB0
 2003 Microchip Technology Inc.
overhead
a
Power-on
0000 000x 0000 000u
-000 0000 -000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 00-0 0000 00-0
0000 ---- 0000 ----
-111 1111 -111 1111
xxxx 0000
xxx0 0000
xxxx xxxx
00xx xxxx
1111 1111 1111 1111
1111 1111 1111 1111
POR, BOR
Value on
(moving
Reset.
uuuu 0000
uuu0 0000
uuuu uuuu
00uu uuuu
Value on
RESETS
all other
The
the

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