PIC16C716-04I/P Microchip Technology, PIC16C716-04I/P Datasheet - Page 5

• Manufacturer Part Number: PIC16C716-04I/P
• Description: IC MCU OTP 2KX14 A/D PWM 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C716-04I/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-DIP (0.300", 7.62mm)
• For Use With: ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMING309-1059 - ADAPTER 18 ZIF BD W/18SO PLUGSDVA16XP180 - ADAPTER DEVICE FOR MPLAB-ICEAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

2.
Code Example:
**************************************************************************************
;
;
;
;
;
TMR1Capture
 2003 Microchip Technology Inc.
Module: Timer1
When Timer1 is configured to operate as an
asynchronous counter, care must be taken that
there is no incoming pulse while the module is
being turned off. If an incoming pulse arrives while
Timer1 is being turned off (i.e., TMR1ON transi-
tions from 1 to 0), the value of registers TMR1L
and TMR1H will be unpredictable.
Work around
This solution involves changing Timer1 from
Asynchronous to Synchronous mode before turn-
ing off Timer1. No additional resources are
required for this solution.
Call this routine to stop Timer1 asynchronous counting
Timer1 is stopped after the timer is changed to synchronous mode
The captured timer value resides in TMR1H and TMR1L at the completion of this
routine.
bcf
bcf
bsf
return
T1CON,NOT_T1SYNC
T1CON,TMR1ON
T1CON,NOT_T1SYNC
; entry point
; set for synchronous mode
; stop timer
; restore asynchronous mode
; return to calling routine
Timer1 synchronization will start, effectively stop-
ping Timer1, one Q period after the Synchronous
mode is enabled, or one Q period later than would
have been realized by simply clearing the
TMR1ON bit. One additional count, in excess of
the counts accrued during this extra Q period, may
be accumulated before the TMR1ON bit is eventu-
ally cleared in the next instruction. The occurrence
of this additional count is dependent on the phase
relationship between OSC1, or the internal system
clock, and T1CKI.
PIC16C712/716
DS80072D-page 5