PIC18F2221-I/SO Microchip Technology, PIC18F2221-I/SO Datasheet - Page 145

• Manufacturer Part Number: PIC18F2221-I/SO
• Description: IC PIC MCU FLASH 2KX16 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2221-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 4KB (2K x 16)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, ICE2000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

16.0
PIC18F2221/2321/4221/4321 family devices all have
two CCP (Capture/Compare/PWM) modules. Each
module contains a 16-bit register which can operate as
a 16-bit Capture register, a 16-bit Compare register or
a PWM Master/Slave Duty Cycle register.
In 28-pin devices, the two standard CCP modules
(CCP1 and CCP2) operate as described in this
chapter. In 40/44-pin devices, CCP1 is implemented
as an Enhanced CCP module with standard Capture
and Compare modes and Enhanced PWM modes.
The
Section 17.0 “Enhanced Capture/Compare/PWM
(ECCP) Module”.
REGISTER 16-1:
© 2009 Microchip Technology Inc.
ECCP
CAPTURE/COMPARE/PWM
(CCP) MODULES
bit 7-6
bit 5-4
bit 3-0
implementation
CCPxCON REGISTER (CCP2 MODULE, CCP1 MODULE IN 28-PIN DEVICES)
PIC18F2221/2321/4221/4321 FAMILY
Unimplemented: Read as ‘0’
DCxB<1:0>: PWM Duty Cycle bit 1 and bit 0 for CCP Module x
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight MSbs
(DCxB<9:2>) of the duty cycle are found in CCPRxL.
CCPxM<3:0>: CCPx Module Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCP module)
0001 = Reserved
0010 = Compare mode, toggle output on match (CCPxIF bit is set)
0011 = Reserved
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode: initialize CCP pin low; on compare match, force CCP pin high
1001 = Compare mode: initialize CCP pin high; on compare match, force CCP pin low
1010 = Compare mode: generate software interrupt on compare match (CCPxIF bit is set,
1011 = Compare mode: trigger special event, reset timer, start A/D conversion on
11xx = PWM mode
bit 7
Legend:
R = Readable bit
-n = Value at POR
U-0
—
(CCPxIF bit is set)
(CCPxIF bit is set)
CCP pin reflects I/O state)
CCPx match (CCPxIF bit is set)
is
U-0
discussed
—
DCxB1
R/W-0
W = Writable bit
‘1’ = Bit is set
in
DCxB0
R/W-0
The Capture and Compare operations described in this
chapter apply to all standard and Enhanced CCP
modules.
Note: Throughout this section and Section 17.0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
“Enhanced Capture/Compare/PWM (ECCP)
Module”, references to the register and bit
names for CCP modules are referred to
generically by the use of ‘x’ or ‘y’ in place
of the specific module number. Thus,
“CCPxCON” might refer to the control regis-
ter for CCP1, CCP2 or ECCP1. “CCPxCON”
is used throughout these sections to refer to
the module control register, regardless of
whether the CCP module is a standard or
Enhanced implementation.
CCPxM3
R/W-0
CCPxM2 CCPxM1 CCPxM0
R/W-0
x = Bit is unknown
R/W-0
DS39689F-page 145
R/W-0
bit 0