PIC16F1937-I/ML Microchip Technology, PIC16F1937-I/ML Datasheet - Page 10

• Manufacturer Part Number: PIC16F1937-I/ML
• Description: IC PIC MCU FLASH 512KX14 44-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1937-I/ML

• Core Size: 8-Bit
• Program Memory Size: 14KB (8K x 14)
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Controller Family/series: PIC16F
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Shifts are similar to rotates with the exception that the
incoming digit is not drawn from the Carry flag but it is
either a ‘0’ or a sign extension. An arithmetic shift per-
forms sign extension, while logical shifts bring in zero.
Sign extension means the Most Significant bit (MSb) is
duplicated. This is a very useful feature because a neg-
ative number that is right shifted remains a negative
number. If a multi-byte value is being shifted, then the
first byte is shifted and the remaining bytes are rotated.
That will utilize the Carry flag correctly so all the bits
propagate across the bytes. Rotates and Shifts are now
more functional because the W register is mapped as
the file register WREG. This allows rotates and shifts to
directly operate on the W register.
TABLE 3:
Table 3 above shows the differences between the
different shift operations.
Interrupts
Interrupts on the enhanced PIC12/16 are essentially
unchanged but for the addition of a hardware context-
save. This reduces the interrupt overhead by
eliminating the essential task of saving key registers
such as the W, or STATUS at the beginning of the
Interrupt Service Routine (ISR) and restoring them at
the end.
DS41375A-page 10
Starting Value
0x7F
0x80
0x7F
0x80
0x7F
0x80
LOGICAL SHIFT OPERATIONS
LSLF/ASLF
LSLF/ASLF
Operation
ASRF
ASRF
LSRF
LSRF
0xC0, C = 0
0xFE, C = 0
0x40, C = 0
Final Value
0x00, C = 1
0x3F, C = 1
0x3F, C = 1
HARDWARE CONTEXT SAVING
The hardware context-save system consists of a
number of registers located in Bank 31. These registers
contain the backup copy of the saved context and are
the source of the restored context. The registers saved
are shown in Table 4.
TABLE 4:
If the context needs to be dynamically adjusted, then
the context-save registers are necessary to accomplish
this.
Register
STATUS
PCLATH
FSR0H
FSR1H
WREG
FSR0L
FSR1L
BSR
HARDWARE CONTEXT
SHADOW LOCATIONS
Context-Saved
STATUS_SHAD
PCLATH_SHAD
FSR0L_SHAD
FSR0H_SHAD
FSR1L_SHAD
FSR1H_SHAD
WREG_SHAD
BSR_SHAD
Register
© 2009 Microchip Technology Inc.
Address
Bank 31
0xFEA
0xFEB
0xFE5
0xFE4
0xFE8
0xFE9
0xFE6
0xFE7