ATTINY2313V-10MU Atmel, ATTINY2313V-10MU Datasheet - Page 171

• Manufacturer Part Number: ATTINY2313V-10MU
• Description: 10MHZ MLF IND TEMP GREEN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY2313V-10MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-MLF®, QFN
• Processor Series: ATTINY2x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: SPI/UART/USI
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q2312268B

2543L–AVR–08/10
Figure 77. Parallel Programming Timing, Reading Sequence (within the Same Page) with Tim-
ing Requirements
Note:
Table 76. Parallel Programming Characteristics, V
Symbol
V
I
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
PP
DVXH
XLXH
XHXL
XLDX
XLWL
XLPH
PLXH
BVPH
PHPL
PLBX
WLBX
PLWL
BVWL
WLWH
WLRL
WLRH
WLRH_CE
XLOL
PP
XTAL1
DATA
BS1
XA0
XA1
OE
1. The timing requirements shown in
ing operation.
Parameter
Programming Enable Voltage
Programming Enable Current
Data and Control Valid before XTAL1 High
XTAL1 Low to XTAL1 High
XTAL1 Pulse Width High
Data and Control Hold after XTAL1 Low
XTAL1 Low to WR Low
XTAL1 Low to PAGEL high
PAGEL low to XTAL1 high
BS1 Valid before PAGEL High
PAGEL Pulse Width High
BS1 Hold after PAGEL Low
BS2/1 Hold after WR Low
PAGEL Low to WR Low
BS1 Valid to WR Low
WR Pulse Width Low
WR Low to RDY/BSY Low
WR Low to RDY/BSY High
WR Low to RDY/BSY High for Chip Erase
XTAL1 Low to OE Low
(1)
ADDR0 (Low Byte)
LOAD ADDRESS
(LOW BYTE)
t
XLOL
t
OLDV
(1)
DATA (Low Byte)
READ DATA
(LOW BYTE)
Figure 75
CC
t
(2)
BVDV
(i.e., t
= 5V ± 10%
DVXH
(HIGH BYTE)
11.5
Min
150
150
READ DATA
200
150
150
3.7
7.5
67
67
67
67
67
67
67
DATA (High Byte)
0
0
0
0
, t
XHXL
Typ
, and t
t
OHDZ
XLDX
Max
12.5
250
4.5
1
9
LOAD ADDRESS
(LOW BYTE)
) also apply to read-
ADDR1 (Low Byte)
Units
μA
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
V
171