PIC18F24K20-E/SO Microchip Technology, PIC18F24K20-E/SO Datasheet - Page 20

• Manufacturer Part Number: PIC18F24K20-E/SO
• Description: IC PIC MCU FLASH 8KX16 28-SOIC
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F24K20-E/SO

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 64MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: CCP, ECCP, EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F2XK20/4XK20
3.3
Data EEPROM is accessed one byte at a time via an
Address Pointer (register pair EEADRH:EEADR) and a
data latch (EEDATA). Data EEPROM is written by
loading EEADRH:EEADR with the desired memory
location, EEDATA with the data to be written and initiat-
ing a memory write by appropriately configuring the
EECON1 register. A byte write automatically erases the
location and writes the new data (erase-before-write).
When using the EECON1 register to perform a data
EEPROM write, both the EEPGD and CFGS bits must
be cleared (EECON1<7:6> = 00). The WREN bit must
be set (EECON1<2> = 1) to enable writes of any sort
and this must be done prior to initiating a write
sequence. The write sequence is initiated by setting the
WR bit (EECON1<1> = 1).
The write begins on the falling edge of the 24th PGC
after the WR bit is set. It ends when the WR bit is
cleared by hardware.
After the programming sequence terminates, PGC
must be held low for the time specified by parameter
P10 to allow high-voltage discharge of the memory
array.
FIGURE 3-7:
DS41297F-page 20
PGC
PGD
Poll WR bit
Data EEPROM Programming
4-bit Command
1
0
2
0
3
0
4
PGD
0
PGC
P5
DATA EEPROM WRITE TIMING DIAGRAM
BSF EECON1, WR
1
4-bit Command
2
1
0
2
0
15 16
3
0
4
0
P5A
P5
MOVF EECON1, W, 0
2 NOP commands
1
Advance Information
2
PGD = Input
PGD = Input
15 16
P5A
P5A
4-bit Command
1
0
FIGURE 3-6:
2
0
3
0
4
0
Poll WR bit, Repeat until Clear
P5
MOVWF TABLAT
1
(see below)
No
2
P11A
15 16
PROGRAM DATA FLOW
Enable Write
Set Address
Start Write
Sequence
© 2009 Microchip Technology Inc.
Set Data
done?
WR bit
clear?
Start
Done
P5A
Yes
Yes
(see Figure 4-4)
PGD = Output
Shift Out Data
No
P10
16-bit Data
Payload
1
n
2
n