PIC12C672-04/P Microchip Technology, PIC12C672-04/P Datasheet - Page 73

• Manufacturer Part Number: PIC12C672-04/P
• Description: IC MCU OTP 2KX14 A/D 8DIP
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12C672-04/P

• Core Size: 8-Bit
• Program Memory Size: 3.5KB (2K x 14)
• Core Processor: PIC
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Controller Family/series: PIC12
• No. Of I/o's: 6
• Ram Memory Size: 128Byte
• Cpu Speed: 4MHz
• No. Of Timers: 1
• Digital Ic Case Style: DIP
• Processor Series: PIC12C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 8
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMINGAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

4.2
1997 Microchip Technology Inc.
OSC2/CLKOUT
(RC mode)
Clocking Scheme/Instruction Cycle
OSC1
Q4
PC
Q2
Q3
Q1
The clock input (from OSC1) is internally divided by four to generate four non-overlapping
quadrature clocks, namely Q1, Q2, Q3, and Q4. Internally, the program counter (PC) is incre-
mented every Q1, and the instruction is fetched from the program memory and latched into the
instruction register in Q4. The instruction is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow are illustrated in
Example
Figure 4-3: Clock/Instruction Cycle
Q1
Execute INST (PC-1)
Fetch INST (PC)
Q2
T
4-1.
CY
PC
1
Q3
Q4
Q1
Execute INST (PC)
Fetch INST (PC+1)
Section 4. Architecture
Q2
T
PC+1
CY
2
Q3
Q4
Q1
Execute INST (PC+1)
Fetch INST (PC+2)
Q2
T
PC+2
CY
3
Q3
Q4
DS31004A-page 4-5
Figure
Internal
phase
clock
4-3, and
4