PIC18F13K50-I/SS Microchip Technology, PIC18F13K50-I/SS Datasheet - Page 4

• Manufacturer Part Number: PIC18F13K50-I/SS
• Description: IC PIC MCU FLASH 8KB 20-SSOP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F13K50-I/SS

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 20-SSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 14
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: EUSART, I2C, MSSP, SPI, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM164127, DV164126
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Package: 20SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164126 - KIT DEVELOPMENT USB W/PICKIT 2DM164127 - KIT DEVELOPMENT USB 18F14/13K50AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPXLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC164307 - MODULE SKT FOR PM3 28SSOP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F1XK50/PIC18LF1XK50
2. Module: MSSP (Master Synchronous
3. Module: System Clocks
1.
2.
3.
4.
DS80411C-page 4
When the SPI clock is configured for Timer2/2
(SSPCON1<3:0> = 0011), the first SPI high time
may be short.
Affected Silicon Revisions
3.1
HFINTOSC output frequency may have up to 1%
short term frequency instability.
Work around
Use the HS, XT or EC clock modes.
Affected Silicon Revisions
3.2
The internal oscillator module may experience a
±1% frequency shift after a Reset. The frequency
shift is not consistent and could cause the
oscillator
specification.
Work around
To minimize the chances of experiencing the
frequency shift, the following steps should be
taken:
Operate the internal oscillator at 8 MHz or 2
MHz.
Use an external pull-up on MCLR or use internal
MCLR mode.
Disable the Power Reset Timer (PWRT).
The bypass capacitor and Voltage Regulator
Capacitor (V
to minimize noise in the device.
Affected Silicon Revisions
A6
A6
A6
X
X
X
Option 1: Ensure TMR2 value rolls over to
Option 2: Turn Timer2 off and clear TMR2
Work around
Frequency Instability
Frequency Shift on Reset
A7
A7
A7
X
X
Serial Port)
to
CAP
A8
A8
A8
X
operate
) should be used appropriately
zero immediately before writing to
SSPBUF.
before writing SSPBUF. Enable
TMR2 after SSPBUF is written.
outside
of
the
2%
4. Module: Timer1
5. Module: EUSART
At minimum V
up to 100°C, not above.
Work around
None.
Affected Silicon Revisions
5.1
In Asynchronous Receive mode, the RCIDL bit of
the BAUDCON register will properly go low when
the RX input goes low at the leading edge of a Start
bit. If the RX input stays low for less than 1/8
bit time, then the Start bit is invalid and the RCIDL
should go high. However, the RCIDL bit will stay
low improperly until a valid Start bit is received.
Work around
When monitoring the RCIDL bit, measure the
length of time between the RCIDL going low and
the RCIF flag going high. If this time is greater than
one character time, then restore the RCIDL bit by
resetting the EUSART module. The EUSART
module is reset when the SPEN bit of the RCSTA
register is cleared.
Affected Silicon Revisions
5.2
The OERR flag of the RCSTA register is reset only
by clearing the CREN bit of the RCSTA register or
by a device Reset. Clearing the SPEN bit of the
RCSTA register does not clear the OERR flag.
Work around
Clear the OERR flag by clearing the CREN bit
instead of clearing the SPEN bit.
Affected Silicon Revisions
A6
A6
A6
X
X
X
RCIDL Bit
OERR Bit
A7
A7
A7
X
X
A8
A8
A8
DD
X
(1.8V) Timer1 will work, but only
 2010 Microchip Technology Inc.
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