z80230 ZiLOG Semiconductor, z80230 Datasheet
z80230
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z80230 Summary of contents
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... GENERAL DESCRIPTION The Zilog Enhanced Serial Communications Controller, Z80230 ESCC pin and software compatible CMOS member of the SCC family introduced by Zilog in 1981. The ESCC is a dual-channel, full-duplex data communications controller capable of supporting a wide range of popular protocols. The ESCC is built from Zilog’s industry standard SCC core and is compatible with designs using Zilog’ ...
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... NC 17 /RTxCB RxDB /TRxCB TxDB /DTR//REQB RTSB /CTSB /DCDB Z80230 Z80230 PLCC Pin Assignments R//W /CS0 /CS1 NC GND /W//REQB /SYNCB /RTxCB RxDB /TRxCB TxDB ...
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ABSOLUTE MAXIMUM RATINGS V Supply Voltage range ......................... -0.3V to +7.0V CC Voltages on all pins with respect to GND ........................ -0. Operating Ambient Temperature......................... See Ordering Information Storage Temperature ............................ - +150 C STANDARD TEST ...
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... DC CHARACTERISTICS Z80230 Symbol Parameter V Input High Voltage IH V Input Low Voltage IL V Output High Voltage OH1 V Output High Voltage OH2 V Output Low Voltage OL I Input Leakage IL I Output Leakage Supply Current CC1 CC I Crystal OSC Current CC(OSC) Notes: [ 10% unless otherwise specified, over specified temperature range. ...
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... AC CHARACTERISTICS Z80230 Read and Write Timing Diagrams /AS 1 /CS0 3 CS1 /INTACK 7 R//W Read R//W Write /DS AD7-AD0 Write 15 AD7-AD0 Read 15 /W//REQ Wait /W//REQ Request /DTR//REQ Request /INT PCLK Z80230 Read/Write Timing Diagram ...
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... AD7-AD0 IEI 34 IEO /INT Z80230 Interrupt Acknowledge Timing Diagram / Z80230 Reset Timing Diagram Active Valid ...
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... AC CHARACTERISTICS Z80230 Read/Write Timing Table No Symbol Parameter 1 TwAS /AS Low Width 2 TdDS(AS) /DS Rise to /AS Fall Delay 3 TsCSO(AS) /CS0 to /AS Rise Setup Time 4 ThCSO(AS) /CS0 to /AS Rise Hold Time 5 TsCS1(DS) CS1 to /DS Fall Setup Time 6 ThCS1(DS) CS1 to /DS Rise Hold Time 7 TslA(AS) /INTACK to /AS Rise Setup Time ...
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... AC CHARACTERISTICS Z80230 Read/Write Timing Table (Continued) No Symbol Parameter 41 TwPCh PCLK High Width 42 TcPC PCLK Cycle Time 43 TrPC PCLK Rise Time 44 TfPC PCLK Fall Time Notes: [1] Parameter does not apply to Interrupt Acknowledge transactions. [2] Parameter applies only between transactions involving the SCC. [3] Float delay is defined as the time required for a 0.5V change in the output with a maximum DC load and a minimum AC load. ...
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... Request /W//REQ Wait /CTS//TRxC, RTxC Receive 4 RxD 8 /SYNC External /CTS//TRxC, RTxC Transmit TxD 13 /CTS//TRxC Output /RTxC /CTS//TRxC /CTS//TRxC, /DCD /SYNC Input Z80230 General Timing Diagram ...
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... AC CHARACTERISTICS Z80230 General Timing Table No Symbol Parameter 1 TdPC(REQ) /PCLK Low to W/REQ Valid 2 TsPC(W) /PCLK Low to Wait Inactive 3 TsRXC(PC) /RxC High to /PCLK High Setup Time 4 TsRXD(RXCr) RxD to /RxC High Setup Time 5 ThRXD(RxCr) RxD to /RxC High Hold Time 6 TsRXD(RXCf) RxD to /RxC Low Setup Time ...
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... AC CHARACTERISTICS Z80230 System Timing Diagram /RTxC, /TRxC Receive /W//REQ Request /W//REQ Wait /SYNC Output /INT /TRxC, /RTxC Transmit /W//REQ Request /W//REQ Wait /DTR//REQ Request /INT /CTS, /DCD /SYNC Input /INT Z80230 System Timing Diagram 11 ...
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... AC CHARACTERISTICS Z80230 System Timing Table No Symbol Parameter 1 TdRXC(REQ) /RxC High to W/REQ Valid 2 TdRXC(W) /RxC High to Wait Inactive 3 TdRdXC(SY) /RxC High to SYNC Valid 4b TdRXC(INT), Z80230 /RxC High to INT Valid 5 TdTXC(REQ) /TxC Low to W/REQ Valid 6 TdTXC(W) /TxC Low to Wait Inactive 7 TdTXC(DRQ) /Txc Low to DTR/REQ Valid ...