MM74HCT00M Fairchild Semiconductor, MM74HCT00M Datasheet

IC GATE NAND QUAD 2-INP 14-SOIC

MM74HCT00M

Manufacturer Part Number
MM74HCT00M
Description
IC GATE NAND QUAD 2-INP 14-SOIC
Manufacturer
Fairchild Semiconductor
Series
74HCTr
Datasheet

Specifications of MM74HCT00M

Logic Type
NAND Gate
Number Of Inputs
2
Number Of Circuits
4
Current - Output High, Low
4.8mA, 4.8mA
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Product
NAND
Logic Family
74HC
High Level Output Current
- 4.8 mA
Low Level Output Current
4.8 mA
Propagation Delay Time
23 ns
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Part Number
Manufacturer
Quantity
Price
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©1984 Fairchild Semiconductor Corporation
MM74HCT00 Rev. 1.3.0
MM74HCT00
Quad 2 Input NAND Gate
Features
Ordering InformationOrdering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Connection Diagram
MM74HCT00M
MM74HCT00SJ
MM74HCT00MTC
MM74HCT00N
Order Number
Pin Assignments for DIP, SOIC, SOP and TSSOP
TTL, LS pin-out and threshold compatible
Fast switching: t
Low power: 10µW at DC
High fan out, 10 LS-TTL loads
All packages are lead free per JEDEC: J-STD-020B standard.
PLH
Package
Number
, t
MTC14
M14A
M14D
N14A
Top View
PHL
14ns (typ.)
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
General Description
The MM74HCT00 is a NAND gates fabricated using
advanced silicon-gate CMOS technology which provides
the inherent benefits of CMOS—low quiescent power
and wide power supply range. This device is input and
output characteristic and pin-out compatible with stan-
dard 74LS logic families. All inputs are protected from
static discharge damage by internal diodes to V
ground.
MM74HCT devices are intended to interface between
TTL and NMOS components and standard CMOS
devices. These parts are also plug-in replacements for
LS-TTL devices and can be used to reduce power
consumption in existing designs.
Logic Diagram
Package Description
(1 of 4 gates)
February 2008
www.fairchildsemi.com
CC
and

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MM74HCT00M Summary of contents

Page 1

... Package Order Number Number MM74HCT00M M14A MM74HCT00SJ M14D MM74HCT00MTC MTC14 MM74HCT00N N14A Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. Connection Diagram Pin Assignments for DIP, SOIC, SOP and TSSOP Top View © ...

Page 2

... Symbol V Supply Voltage Input or Output Voltage IN OUT T Operating Temperature Range Input Rise or Fall Times r f ©1984 Fairchild Semiconductor Corporation MM74HCT00 Rev. 1.3.0 (1) Parameter Parameter 2 Rating –0.5 to +7.0V –1 +1.5V CC –0 +0.5V CC ±20mA ±25mA ±50mA –65°C to +150°C ...

Page 3

... Minimum HIGH Level OH Output Voltage V Maximum LOW Level OL Voltage I Maximum Input IN Current I Maximum Quiescent CC Supply Current Note: 3. This is measured per input with all other inputs held at V ©1984 Fairchild Semiconductor Corporation MM74HCT00 Rev. 1.3.0 T 25°C A Conditions Typ. 2.0 0 – 0.1 IN ...

Page 4

... Maximum Output Rise and THL TLH Fall Time C Power Dissipation PD Capacitance C Input Capacitance IN Note determines the no load dynamic power consumption current consumption ©1984 Fairchild Semiconductor Corporation MM74HCT00 Rev. 1.3.0 = 25°C (unless otherwise noted) A Conditions = 50pF (unless otherwise noted Conditions Typ ( ...

Page 5

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 6

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 7

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 8

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 9

... TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended exhaustive list of all such trademarks. ® ACEx Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ ...

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