MC74ACT273 ON Semiconductor, MC74ACT273 Datasheet

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MC74ACT273

Manufacturer Part Number
MC74ACT273
Description
Octal D Flip-Flop
Manufacturer
ON Semiconductor
Datasheet

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MC74AC273, MC74ACT273
Octal D Flip−Flop
flip−flops with individual D inputs and Q outputs. The common
buffered Clock (CP) and Master Reset (MR) inputs load and reset
(clear) all flip−flops simultaneously.
setup time before the LOW−to−HIGH clock transition, is transferred
to the corresponding flip−flop’s Q output.
inputs by a LOW voltage level on the MR input. The device is useful
for applications where the true output only is required and the Clock
and Master Reset are common to all storage elements.
Features
*For additional information on our Pb−Free strategy and soldering details, please
© Semiconductor Components Industries, LLC, 2005
December, 2005 − Rev. 6
MODE SELECT-FUNCTION TABLE
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Reset (Clear)
Load ′1′
Load ′0′
The MC74AC273/74ACT273 has eight edge-triggered D−type
The register is fully edge-triggered. The state of each D input, one
All outputs will be forced LOW independently of Clock or Data
Ideal Buffer for MOS Microprocessor or Memory
Eight Edge-Triggered D Flip−Flops
Buffered Common Clock
Buffered, Asynchronous Master Reset
See MC74AC377 for Clock Enable Version
See MC74AC373 for Transparent Latch Version
See MC74AC374 for 3-State Version
Outputs Source/Sink 24 mA
′ACT273 Has TTL Compatible Inputs
Pb−Free Packages are Available*
= LOW-to-HIGH Clock Transition
Operating Mode
V
MR
20
1
CC
Pinout: 20−Lead Packages Conductors
Q
Q
19
2
7
0
D
D
18
3
7
0
D
D
17
4
6
1
MR
H
H
(Top View)
L
Q
Q
16
5
6
1
Inputs
CP
Q
Q
X
15
6
5
2
D
D
D
14
X
H
L
7
5
2
n
Outputs
D
13
D
8
4
3
Q
H
L
L
n
Q
12
Q
9
4
3
GND
CP
11
10
1
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
See general marking information in the device marking
section on page 6 of this data sheet.
20
20
20
20
DEVICE MARKING INFORMATION
PIN
D
MR
CP
Q
0
0
1
−D
−Q
ORDERING INFORMATION
CP
MR
7
7
D
Q
1
http://onsemi.com
1
PIN ASSIGNMENT
0
1
0
D
Q
1
1
Logic Symbol
FUNCTION
Data Inputs
Master Reset
Clock Pulse Input
Data Outputs
D
Q
2
2
D
Q
Publication Order Number:
3
3
D
Q
4
4
D
Q
SOIC−20WB
SUFFIX DW
CASE 751D
CASE 948E
SOEIAJ−20
5
5
TSSOP−20
SUFFIX DT
CASE 738
SUFFIX M
CASE 967
SUFFIX N
PDIP−20
D
Q
MC74AC273/D
6
6
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D
Q
7
7

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