mc74ac74 ON Semiconductor, mc74ac74 Datasheet
mc74ac74
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mc74ac74 Summary of contents
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... MC74AC74, MC74ACT74 Dual D−Type Positive Edge−Triggered Flip−Flop The MC74AC74/74ACT74 is a dual D−type flip−flop with Asynchronous Clear and Set inputs and complementary (Q,Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse ...
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TRUTH TABLE (Each Half) Inputs NOTE HIGH Voltage Level L ...
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RECOMMENDED OPERATING CONDITIONS Symbol V Supply Voltage Input Voltage, Output Voltage (Ref. to GND) in out Input Rise and Fall Time (Note ) ′AC Devices except Schmitt Inputs Input Rise ...
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... AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D) Symbol Parameter Maximum Clock f max Frequency Propagation Delay t PLH Propagation Delay t PHL Propagation Delay t PLH ...
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... Maximum Quiescent CC Supply Current *All outputs loaded; thresholds on input associated with output under test. †Maximum test duration 2.0 ms, one output loaded at a time. AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D) Symbol Parameter Maximum Clock f max ...
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AC OPERATING REQUIREMENTS Symbol Parameter Set-up Time, HIGH or LOW Hold Time, HIGH or LOW Pulse ...
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... MC74ACT74NG MC74AC74D MC74AC74DG MC74AC74DR2 MC74AC74DR2G MC74ACT74D MC74ACT74DG MC74ACT74DR2 MC74ACT74DR2G MC74AC74DT MC74AC74DTR2 MC74AC74DTR2G MC74ACT74DT MC74ACT74DTR2 MC74ACT74DTR2G MC74AC74MEL MC74AC74MELG MC74ACT74MEL MC74ACT74MELG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. ...
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... PDIP−14 SOIC−14 14 MC74AC74N AWLYYWWG AC74G AWLYWW 1 MC74ACT74N 14 AWLYYWWG ACT74G AWLYWW 1 (Note: Microdot may be in either location) MARKING DIAGRAMS TSSOP− ALYWG G ACT 74 ALYWG Assembly Location WL Wafer Lot YY Year WW Work Week Pb−Free Package http://onsemi ...
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−T− SEATING PLANE 0.13 (0.005) PACKAGE DIMENSIONS PDIP−14 CASE 646−06 ISSUE http://onsemi.com 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI ...
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... K D SEATING 14 PL PLANE 0.25 (0.010 14X 0.58 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOIC−14 CASE 751A−03 ISSUE 0.25 (0.010 ...
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... S A −V− C 0.10 (0.004) −T− SEATING G D PLANE 14X 0.36 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS TSSOP−14 CASE 948G−01 ISSUE ...
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... BSC 0.050 BSC H 7.40 8.20 0.291 0.323 E 0.50 0.50 0.85 0.020 0.033 L 1.10 1.50 0.043 0.059 0.70 0.90 0.028 0.035 1 Z −−− 1.42 −−− 0.056 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative MC74AC74/D ...