MC14LC5480 Motorola, MC14LC5480 Datasheet

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MC14LC5480

Manufacturer Part Number
MC14LC5480
Description
5 V PCM Codec-Filter
Manufacturer
Motorola
Datasheet

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Advance Information
5 V PCM Codec-Filter
pin selectable Mu–Law or A–Law companding, and is offered in 20–pin DIP,
SOG, and SSOP packages. This device performs the voice digitization and
reconstruction as well as the band limiting and smoothing required for PCM
systems. This device is designed to operate in both synchronous and
asynchronous applications and contains an on–chip precision reference
voltage.
encoder section. The encoder section immediately low–pass filters the analog
signal with an active R–C filter to eliminate very high frequency noise from being
modulated down to the passband by the switched capacitor filter. From the
active R–C filter, the analog signal is converted to a differential signal. From this
point, all analog signal processing is done differentially. This allows processing
of an analog signal that is twice the amplitude allowed by a single–ended
design, which reduces the significance of noise to both the inverted and
non–inverted signal paths. Another advantage of this differential design is that
noise injected via the power supplies is a common–mode signal that is
cancelled when the inverted and non–inverted signals are recombined. This
dramatically improves the power supply rejection ratio.
passes the analog signal from 200 Hz to 3400 Hz before the signal is digitized
by the differential compressing A/D converter.
converter. The output of the D/A is low–pass filtered at 3400 Hz and sinX/X
compensated by a differential switched capacitor filter. The signal is then filtered
by an active R–C filter to eliminate the out–of–band energy of the switched
capacitor filter.
including Short Frame Sync, Long Frame Sync, IDL, and GCI timing
environments. This device also maintains compatibility with Motorola’s family of
Telecommunication products, including the MC14LC5472 U–Interface Trans-
ceiver, MC145474/75 S/T–Interface Transceiver, MC145532 ADPCM Trans-
coder, MC145422/26 UDLT–1, MC145421/25 UDLT–2, and MC3419/MC33120
SLIC.
low–power performance and proven capability for complex analog/digital VLSI
functions.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 0.1
5/96
MOTOROLA
The MC14LC5480 is a general purpose per channel PCM Codec–Filter with
This device has an input operational amplifier whose output is the input to the
After the differential converter, a differential switched capacitor filter band–
The decoder accepts PCM data and expands it using a differential D/A
The MC14LC5480 PCM Codec–Filter accepts a variety of clock formats,
The MC14LC5480 PCM Codec–Filter utilizes CMOS due to its reliable
Motorola, Inc. 1996
Pin for Pin Replacement for the MC145480
Single 5 V Power Supply
Typical Power Dissipation of 15 mW, Power–Down of 0.01 mW
Fully–Differential Analog Circuit Design for Lowest Noise
Transmit Band–Pass and Receive Low–Pass Filters On–Chip
Active R–C Pre–Filtering and Post–Filtering
Mu–Law and A–Law Companding by Pin Selection
On–Chip Precision Reference Voltage (1.575 V)
Push–Pull 300
MC145536EVK is the Evaluation Kit that Also Includes the MC145532
ADPCM Transcoder
Power Drivers with External Gain Adjust
20
20
20
MC14LC5480
MC14LC5480P
MC14LC5480DW
MC14LC5480SD
1
ORDERING INFORMATION
BCLKR
RO+
RO–
PO+
V DD
PO–
FSR
1
PDI
DR
PI
PIN ASSIGNMENT
1
1
2
3
4
5
6
7
8
9
10
SOG PACKAGE
Order this document
PLASTIC DIP
Plastic DIP
SOG Package
SSOP
DW SUFFIX
CASE 751D
CASE 940C
SD SUFFIX
CASE 738
by MC14LC5480/D
P SUFFIX
20
19
18
17
16
15
14
13
12
11
SSOP
MC14LC5480
V AG
TI+
TI–
TG
Mu/A
V SS
FST
DT
BCLKT
MCLK
1

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MC14LC5480 Summary of contents

Page 1

... SEMICONDUCTOR TECHNICAL DATA Advance Information 5 V PCM Codec-Filter The MC14LC5480 is a general purpose per channel PCM Codec–Filter with pin selectable Mu–Law or A–Law companding, and is offered in 20–pin DIP, SOG, and SSOP packages. This device performs the voice digitization and reconstruction as well as the band limiting and smoothing required for PCM systems ...

Page 2

... The low–pass filter used to at- tenuate these aliasing components is typically called a re- construction or smoothing filter. The MC14LC5480 PCM Codec–Filter has the codec, both presampling and reconstruction filters, a precision voltage reference on–chip, and requires no external components. ...

Page 3

... PO+. The PO+ and PO– outputs are differential (push–pull) and capable of driving a 300 3.15 V peak, which is 6.3 V peak–to–peak. The bias voltage and signal reference of this output is the V AG pin. The V AG pin cannot source or sink as much current as this pin, and load to MC14LC5480 3 ...

Page 4

... PCM data. When operating in the IDL or GCI mode, data is output in either the channel as selected by FSR. This pin is high impedance when the device is in the powered down mode. MC14LC5480 4 FSR Frame Sync, Receive (Pin 7) When used in the Long Frame Sync or Short Frame Sync mode, this pin accepts an 8 kHz clock, which synchronizes the input of the serial PCM data at the DR pin ...

Page 5

... RO+ and RO– pins. These outputs are capable of driving differentially load to the V AG pin. The MC14LC5480 also has a pair of power amplifiers that are connected in a push–pull configuration. The PI pin is the inverting input to the PO– ...

Page 6

... Figure 2c. IDL Interface — BCLKR = 1 (Transmit and Receive Have Common Clocking) FSC (FST) DCL (BCLKT) D out (DT) 1 DON’ (DR) 1 CARE B1–CHANNEL (FSR = 0) Figure 2d. GCI Interface — BCLKR = 0 (Transmit and Receive Have Common Clocking) Figure 2. Digital Timing Modes for the PCM Data Interface MC14LC5480 ...

Page 7

... FST, FSR, BCLKT, DT, and DR. The IDL Interface consists of four pins: IDL SYNC (FST), IDL CLK (BCLKT), IDL TX (DT), and IDL RX (DR). The IDL interface mode provides access to both the transmit and receive PCM data words with common control clocks of IDL Sync and IDL Clock. In this mode, the MC14LC5480 7 ...

Page 8

... DCL rising edge after the FSC rising edge. PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS The MC14LC5480 is manufactured using high–speed CMOS VLSI technology to implement the complex analog signal processing functions of a PCM Codec–Filter. The ful- ly–differential analog circuit design techniques used for this device result in superior performance for the switched capac- itor filters, the analog– ...

Page 9

... The MC14LC5480 is fabricated with advanced high– speed CMOS technology that is capable of responding to noise pulses on the clock pins less. It should be noted that noise pulses of such short duration may not be seen with oscilloscopes that have less bandwidth than 600 MHz ...

Page 10

... Input High Current ( Output Current in High Impedance State (V SS Input Capacitance of Digital Pins (Except DT) Input Capacitance of DT Pin when High–Z NOTE: Bold type indicates a change from the MC145480 to the MC14LC5480. MC14LC5480 10 Symbol Min 4.75 (No Load – 0.5 V) — ...

Page 11

... Total Signal to Distortion at PO+ and PO– with a 300 Power Supply Rejection Ratio ( kHz @ 100 mVrms Applied PO– Connected to PI. Differential or Measured Referenced Pin.) NOTE: Bold type indicates a change from the MC145480 to the MC14LC5480. MOTOROLA ( 5 – Min TI+, TI– ...

Page 12

... Range 300 to 3400 Hz) NOTES: 1. Extrapolated from a 1020 Hz @ – 50 dBm0 distortion measurement to correct for encoder enhancement. 2. Selectively measured while stimulated with 2667 Hz @ – 50 dBm0. 3. Bold type indicates a change from the MC145480 to the MC14LC5480. MC14LC5480 12 End–to–End ...

Page 13

... MC14LC5480 13 ...

Page 14

... MCLK 1 BCLKT 11 FST 16 MSB DT 1 BCLKR 11 12 FSR MSB DR MC14LC5480 CH1 CH2 CH3 ST1 CH1 CH2 CH3 ST1 Figure 3. Long Frame Sync Timing ST2 ST3 ...

Page 15

... DT 1 BCLKR FSR 13 MSB DR MOTOROLA CH1 CH2 CH3 ST1 CH1 CH2 CH3 ST1 Figure 4. Short Frame Sync Timing ST2 ST3 LSB ST2 ST3 LSB MC14LC5480 15 ...

Page 16

... IDLE SYNC (FST IDL CLOCK (BCLKT IDL TX MSB CH1 CH2 CH3 (DT IDL RX MSB CH1 CH2 CH3 (DR) MC14LC5480 16 Characteristics ST1 ST2 ST3 LSB MSB CH1 CH2 CH3 38 37 ...

Page 17

... Max Unit Note 2 512 6176 kHz 50 — — — — ns — — — — ns — CH3 ST1 ST2 ST3 LSB 53 CH3 ST1 ST2 ST3 LSB MC14LC5480 17 ...

Page 18

... Figure 7. MC14LC5480 Test Circuit with Differential Input and Output AUDIO OUT AUDIO OUT 150 0.1 F Figure 8. MC14LC5480 Test Circuit with Input and Output Referenced MC14LC5480 RO RO– TI TI– ...

Page 19

... 1/2 MC74HC73 K GND 8 kHz 256 2.048 MHz Figure 9. Long Frame Sync Clock Circuit for 2.048 MHz SIDETONE REC + Figure 10. MC14LC5480 Analog Interface to Handset with IDL Clocking MOTOROLA 2.048 MHz 300 R OSC IN OSC OSC OUT 1 OUT 2 MC74HC4060 ...

Page 20

... R0 = 600 TIP RING + 5 V 0.1 F Figure 11. MC14LC5480 Transformer Interface to 600 R0 = 600 TIP N = 0.5 1 0.5 – 0.5 RING 0.1 F Figure 12. MC14LC5480 Step–Up Transformer Interface to 600 MC14LC5480 RO– TI TI– 4 PO– Mu/A PO+ ...

Page 21

... Normalized Decode Step Step Step Levels 8031 4191 2079 1023 495 231 MC14LC5480 21 ...

Page 22

... NOTES: 1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values. 2. Digital code includes inversion of all even numbered bits. MC14LC5480 22 Digital Code Sign Chord Chord Chord Step ...

Page 23

... TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 12.65 12.95 0.499 0.510 B 7.40 7.60 0.292 0.299 C 2.35 2.65 0.093 0.104 D 0.35 0.49 0.014 0.019 F 0.50 0.90 0.020 0.035 G 1.27 BSC 0.050 BSC _ J 0.25 0.32 0.010 0.012 K 0.10 0.25 0.004 0.009 10.05 10.55 0.395 0.415 R 0.25 0.75 0.010 0.029 MC14LC5480 23 ...

Page 24

... BE 0.08MM TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 7.10 7.30 0.280 0.287 B 5.20 5.38 0.205 0.212 C 1.75 1.99 0.069 0.078 D 0.25 0.38 0.010 0.015 F 0.65 1.00 0.026 0.039 G 0.65 BSC 0.026 BSC H 0.59 0.75 0.023 0.030 J 0.10 0.20 0.004 0.008 L 7.65 7.90 0.301 0.311 0.05 0.21 0.002 0.008 MC14LC5480/D MOTOROLA ...

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