MC10EP445 ON Semiconductor, MC10EP445 Datasheet
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MC10EP445
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MC10EP445 Summary of contents
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... MC10EP445, MC100EP445 3.3V/5V ECL 8−Bit Serial/Parallel Converter Description The MC10/100EP445 is an integrated 8–bit differential serial to parallel data converter with asynchronous data synchronization. The device has two modes of operation. CKSEL HIGH mode is designed to operate NRZ data rates 3.3 Gb/s, while CKSEL LOW mode is designed to operate at twice the internal clock data rate ...
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... Table 2. TRUTH TABLE PIN SINSEL Select SINB Input CKSEL Q: PCLK = 8:1 CLK 1:1 CLK Q CKEN Synchronously Disable Internal Clock Circuitry RESET Asynchronous Master Reset SYNC Asynchronously Applied to Swallow a Data Bit MC10EP445, MC100EP445 Table 1. PIN DESCRIPTION Pin SINA*, SINA SINB*, SINB SINSEL Q0− ...
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... Internal Input Pull−up Resistor ESD Protection Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. MC10EP445, MC100EP445 1:2 DEMUX SYNC Control Logic DIV2 Figure 2. Logic Diagram ...
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... Input and output parameters vary 1:1 with V 3. All loading with − 2 min varies 1:1 with IHCMR EE IHCMR input signal. MC10EP445, MC100EP445 Condition ...
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... Required 500 lfpm air flow when using −5 V power supply. For (V protection at elevated temperatures. Recommend V 11. All loading with − 2 12. V min varies 1:1 with IHCMR EE IHCMR input signal. MC10EP445, MC100EP445 (Note −40°C Min Typ Max Min 95 ...
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... Required 500 lfpm air flow when using +5 V power supply. For (V protection at elevated temperatures. Recommend V 18. All loading with − 2 19. V min varies 1:1 with IHCMR EE IHCMR input signal. MC10EP445, MC100EP445 (Note 13 −40°C Min Typ Max Min 95 ...
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... Measured using a 750 mV source, 50% duty cycle clock source. All loading with 25. V (min) is the minimum input swing for which AC parameters are guaranteed. PP MC10EP445, MC100EP445 −5 −3.0 V (Note 20 − ...
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... MC10EP445, MC100EP445 t Reset CLK CLK Figure 3. Reset Recovery CLK Data Setup Time + Data Hold Time − Figure 4. Data Setup and Hold Time CLK + CKEN Setup Time t CKEN Hold Time − Figure 5. CKEN Setup and Hold Time http://onsemi.com RR − − ...
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... RESET (Asynchronous Reset) CLK RESET PCLK MC10EP445, MC100EP445 APPLICATION INFORMATION The two selectable serial data paths can be used for loop−back testing as well as the bit error testing. Upon power−up, the internal flip−flops will attain a random state. To synchronize multiple flip–flops in the device, the Reset (pin 1) must be asserted ...
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... RESET CKEN CKSEL PCLK Figure 7. Timing Diagram A. 1:8 Serial to Parallel Conversion with CKSEL LOW MC10EP445, MC100EP445 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 Á ...
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... CLK SINA RESET CKEN CKSEL PCLK Figure 8. Timing Diagram A. 1:8 Serial to Parallel Conversion with CKSEL HIGH MC10EP445, MC100EP445 D10 D11 http://onsemi.com 11 D12 D13 D14 Á ...
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... Figure 9. Timing Diagram A. 1:8 Serial to Parallel Conversion with SYNC Pulse at CKSEL LOW MC10EP445, MC100EP445 clock cycles shifts the start bit for conversion from The bit is swallowed following the two clock cycle n−1 pulse width of SYNCÀ on the next triggering edge of clockÁ ...
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... Figure 10. Timing Diagram A. 1:8 Serial to Parallel Conversion with SYNC Pulse at CKSEL HIGH MC10EP445, MC100EP445 triggering edge of clockÁ (on the rising edge of the clock only). Each additional shift requires an additional pulse to be applied to the SYNC pin. (See Figure 10) Next Triggering Edge of Clock ...
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... BB available to this device only. For single–ended input MC10EP445, MC100EP445 edge of CLK will suspend all activities. The first data bit will clock on the rising edge, since the falling edge of CKEN followed by the falling edge of the incoming clock triggers the enabling of the internal process ...
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... MC10EP445, MC100EP445 1000 900 800 700 CKSEL LOW 600 500 400 300 200 (JITTER) É É É É É É É É É É É É É É É É 100 É É É É É É É É É É É É É É É É ...
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... AN1642/D AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices MC10EP445, MC100EP445 Package LQFP−32 LQFP−32 (Pb−Free) LQFP−32 LQFP−32 (Pb− ...
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... DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MC10EP445, MC100EP445 PACKAGE DIMENSIONS 32 LEAD LQFP CASE 873A−02 ISSUE B 4X 0.20 (0.008) AB T− ...
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... P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com MC10EP445, MC100EP445 N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: ...