M24128-BR STMICROELECTRONICS [STMicroelectronics], M24128-BR Datasheet

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M24128-BR

Manufacturer Part Number
M24128-BR
Description
128 Kbit, 64 Kbit and 32 Kbit serial I2C bus EEPROM
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet

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Feature summary
Table 1.
October 2006
M24128
M24C64
M24C32
Reference
Two-Wire I
Supports 400kHz Protocol
Single supply voltages (see
part numbers):
– 2.5 to 5.5V
– 1.8 to 5.5V
– 1.7 to 5.5V
Write Control Input
Byte and Page Write
Random And Sequential Read modes
Self-Timed programming cycle
Automatic address incrementing
Enhanced ESD/Latch-Up Protection
More than 1 Million Write cycles
More than 40-year data retention
Packages
– ECOPACK® (RoHS compliant)
Product list
2
M24128-BW
M24128-BR
M24C64-W
M24C64-R
M24C64-F
M24C32-W
M24C32-R
M24C32-F
Root part number
C serial interface
128 Kbit, 64 Kbit and 32 Kbit serial I²C bus EEPROM
Table 1
2.5 to 5.5V
1.8 to 5.5V
2.5 to 5.5V
1.8 to 5.5V
1.7 to 5.5V
2.5 to 5.5V
1.8 to 5.5V
1.7 to 5.5V
Supply voltage
for root
Rev 9
M24C64 M24C32
UFDFPN8 (MB)
2x3mm² (MLP)
TSSOP8 (DW)
150 mil width
169 mil width
PDIP8 (BN)
SO8 (MN)
M24128
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1/34
1

Related parts for M24128-BR

M24128-BR Summary of contents

Page 1

... Enhanced ESD/Latch-Up Protection More than 1 Million Write cycles More than 40-year data retention Packages – ECOPACK® (RoHS compliant) Table 1. Product list Reference Root part number M24128-BW M24128 M24128-BR M24C64-W M24C64 M24C64-R M24C64-F M24C32-W M24C32 M24C32-R M24C32-F October 2006 Table 1 for root Supply voltage 2 ...

Page 2

... Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 17 4.10 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.11 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.12 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.13 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.14 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2/34 Serial Clock (SCL Serial Data (SDA Operating supply voltage Internal device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 M24128, M24C64, M24C32 ...

Page 3

... M24128, M24C64, M24C32 7 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Contents 3/34 ...

Page 4

... Table 5. Address least significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 6. Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 8. Operating conditions (M24128-BW, M24C64-W, M24C32- Table 9. Operating conditions (M24128-BR, M24C64-R, M24C32- Table 10. Operating conditions (M24C64-F, M24C32- Table 11. AC test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 12. Input parameters Table 13. DC characteristics (V Table 14. ...

Page 5

... M24128, M24C64, M24C32 List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. DIP, SO, TSSOP and UFDFPN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. Maximum RP value versus bus parasitic capacitance (C) for an I2C bus . . . . . . . . . . . . . . 9 2 Figure bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 6. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 7. Write mode sequences with (data write inhibited Figure 8 ...

Page 6

... When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read. 6/34 2 C-compatible electrically erasable M24128-BW M24128-BR E0-E2 M24C64-W M24C64-R SCL M24C64-F M24C32-W WC M24C32-R ...

Page 7

... M24128, M24C64, M24C32 Table 2. Signal names E0, E1, E2 SDA SCL Figure 2. DIP, SO, TSSOP and UFDFPN connections 1. See Package mechanical Chip Enable Serial Data Serial Clock Write Control Supply Voltage Ground M24128 M24C64 M24C32 SCL ...

Page 8

... When Write Control (WC) is driven High, Device Select and Address bytes are acknowledged, Data bytes are not acknowledged. 8/34 indicates how the value of the pull-up resistor can be calculated M24xxx M24xxx M24128, M24C64, M24C32 . (Figure 4 indicates how CC Figure 3. When not connected Ai12806 , and IL ...

Page 9

... M24128, M24C64, M24C32 2.3 Supply voltage (V 2.3.1 Operating supply voltage V Prior to selecting the memory and issuing instructions to it, a valid and stable V within the specified [V In order to secure a stable DC supply voltage recommended to decouple the V with a suitable capacitor (usually of the order of 10nF to 100nF) close to the V package pins ...

Page 10

... SDA SDA START Input Change Condition MSB MSB (1) Device Type Identifier b13 b12 b11 M24128, M24C64, M24C32 STOP Condition ACK ACK STOP Condition (2) Chip Enable Address b10 AI00792B ...

Page 11

... M24128, M24C64, M24C32 3 Memory organization The memory is organized as shown in Figure 6. Block diagram SCL SDA Figure 6. Control Logic I/O Shift Register Address Register and Counter Memory organization High Voltage Generator Data Register 1 Page X Decoder AI06899 11/34 ...

Page 12

... The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The M24C32, M24C64 and M24128 devices are always slaves in all communications. ...

Page 13

... for M24C64 and M24C32 for M24128 Device operation 2 C bus. Each one is given a th bit time. If the device does not match Initial Sequence START, Device Select START, Device Select Address reSTART, Device Select Similar to Current or Random Address ...

Page 14

... BYTE WRITE WC PAGE WRITE WC (cont'd) PAGE WRITE (cont'd) 14/34 ACK ACK DEV SEL BYTE ADDR BYTE ADDR R/W ACK ACK DEV SEL BYTE ADDR BYTE ADDR R/W NO ACK NO ACK DATA IN N M24128, M24C64, M24C32 ACK NO ACK DATA IN ACK NO ACK DATA IN 1 DATA IN 2 AI01120C ...

Page 15

... The Page Write mode allows bytes (for the M24C32 and M24C64 bytes (for the M24128 written in a single Write cycle, provided that they are all located in the same ’row’ in the memory: that is, the most significant memory address bits (b13-b6 for M24128, b12-b5 for M24C64, and b11-b5 for M24C32) are the same. If more bytes are sent than will fit up to the end of the row, a condition known as ‘ ...

Page 16

... BYTE WRITE WC PAGE WRITE WC (cont'd) PAGE WRITE (cont'd) 16/34 ACK ACK DEV SEL BYTE ADDR BYTE ADDR R/W ACK ACK DEV SEL BYTE ADDR BYTE ADDR R/W ACK ACK DATA IN N M24128, M24C64, M24C32 ACK ACK DATA IN ACK ACK DATA IN 1 DATA IN 2 AI01106C ...

Page 17

... M24128, M24C64, M24C32 Figure 9. Write cycle polling flowchart using ACK First byte of instruction with already decoded by the device 4.9 Minimizing system delays by polling on ACK During the internal Write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. The maximum Write time (t ...

Page 18

... BYTE ADDR R/W ACK ACK DEV SEL DATA OUT 1 R/W ACK ACK DEV SEL * BYTE ADDR BYTE ADDR R/W ACK NO ACK DATA OUT N M24128, M24C64, M24C32 ACK ACK NO ACK DEV SEL * DATA OUT R/W ACK NO ACK DATA OUT N ACK ACK ACK DEV SEL * DATA OUT 1 R/W ...

Page 19

... M24128, M24C64, M24C32 4.10 Read operations Read operations are performed independently of the state of the Write Control (WC) signal. After the successful completion of a Read operation, the device’s internal address counter is incremented by one, to point to the next byte address. 4.11 Random Address Read A dummy Write is first performed to load the address into this address counter (as shown in Figure 10) but without sending a Stop condition ...

Page 20

... European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU max must not be applied for more than 10s. LEAD 3. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500 , R2=500 ) 20/34 Table 7 may cause permanent damage to Parameter (3) M24128, M24C64, M24C32 Min. Max. Unit –40 130 °C –65 150 °C (1) see note ° ...

Page 21

... Table 8. Operating conditions (M24128-BW, M24C64-W, M24C32-W) Symbol V Supply Voltage CC Ambient Operating Temperature (Device Grade Ambient Operating Temperature (Device Grade 3) Table 9. Operating conditions (M24128-BR, M24C64-R, M24C32-R) Symbol V Supply Voltage CC T Ambient Operating Temperature A Table 10. Operating conditions (M24C64-F, M24C32-F) Symbol V ...

Page 22

... Stand-by mode OUT SS 2.5V < (rise/fall time < 30ns) During t , 2.5V < 2.1mA 3mA M24128, M24C64, M24C32 Min. Max < 0.3V 50 200 CC > 0.7V 500 CC 200 Min. Table SDA in Hi-Z CC, < 5.5V, f =400kHz c < 5.5V CC ...

Page 23

... M24128, M24C64, M24C32 Table 14. DC characteristics (V Symbol Input Leakage Current I LI (SCL, SDA, E2, E1, E0) I Output Leakage Current LO I Supply Current (Read Supply Current (Write) CC0 I Stand-by Supply Current CC1 Input Low Voltage (SDA SCL, WC) Input High Voltage (SDA, ...

Page 24

... Test Condition Parameter (in addition to those in Table device in Stand-by mode OUT SS V =1.7V (rise/fall time < 30ns) During t , 1.7V < 1.7V < 0.7 mA M24128, M24C64, M24C32 (1) Min. 10 SDA in Hi-Z CC, = 400kHz c < 2. < 2.5V CC –0. Max. ...

Page 25

... M24128, M24C64, M24C32 Table 17. AC characteristics (V Symbol Alt SCL t t CHCL HIGH t t CLCH LOW ( DL1DL2 DXCX SU:DAT t t CLDX HD:DAT t t CLQX DH ( CLQV AA ( CHDX SU:STA t t DLCL HD:STA t t CHDH SU:STO t t DHDL ...

Page 26

... SCL tDLCL SDA In tCHDX START Condition SCL SDA In tCHDH STOP Condition SCL tCLQV SDA Out 26/34 tCLCH tCLDX tDXCX SDA Change SDA Input tW Write Cycle tCLQX Data Valid M24128, M24C64, M24C32 tCHDH tDHDL STOP START Condition Condition tCHDX START Condition AI00795C ...

Page 27

... M24128, M24C64, M24C32 8 Package mechanical Figure 13. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, package outline 1. Drawing is not to scale. Table 19. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, package mechanical data Symbol ...

Page 28

... Typ Min Max 1.75 0.10 0.25 1.25 0.28 0.48 0.17 0.23 0.10 4.90 4.80 5.00 6.00 5.80 6.20 3.90 3.80 4.00 1.27 – – 0.25 0.50 0° 8° 0.40 1.27 1.04 M24128, M24C64, M24C32 h x 45˚ c 0.25 mm GAUGE PLANE SO-A inches Typ Min 0.004 0.049 0.011 0.007 0.193 0.189 0.236 0.228 0.154 0.150 0.050 – 0.010 0° 0.016 0.041 Max 0.069 0.010 0.019 ...

Page 29

... M24128, M24C64, M24C32 Figure 15. TSSOP8 – 8 lead Thin Shrink Small Outline, package outline Drawing is not to scale. Table 21. TSSOP8 – 8 lead Thin Shrink Small Outline, package mechanical data Symbol millimeters Typ ...

Page 30

... A1 millimeters Typ Min Max 0.55 0.50 0.60 0.02 0.00 0.05 0.25 0.20 0.30 2.00 1.90 2.10 1.60 1.50 1.70 0.08 3.00 2.90 3.10 0.20 0.10 0.30 0.50 – – 0.45 0.40 0.50 0.15 0.30 M24128, M24C64, M24C32 UFDFPN-01 inches Typ Min Max 0.022 0.020 0.024 0.001 0.000 0.002 0.010 0.008 0.012 0.079 0.075 0.083 0.063 0.059 0.067 0.003 0.118 0.114 0.122 0.008 0.004 0.012 0.020 – ...

Page 31

... M24128, M24C64, M24C32 9 Part numbering Table 23. Ordering information scheme Example: Device Type 2 M24 = I C serial access EEPROM Device Function 128–B = 128 Kbit (16384 x 8) C64– Kbit (8192 x 8) C32– Kbit (4096 x 8) Operating Voltage 2 1 ...

Page 32

... Product List summary table added. Device Grade 3 added. 4.5-5.5V range is Not for New Design. Some minor wording changes. AEC-Q100- 5.0 002 compliance. t (max) changed pins of the device. Z WCL 6.0 UFDFPN8 package added. Small text changes. M24128, M24C64, M24C32 Changes for E2-E0 and LI (min) improved to -0.45V. IL (min) and V (min) improved ...

Page 33

... Table 13: DC characteristics (VCC = 2.5V to 5.5V, CC1 device grade 6). 8 Note 1 added to Table 16: DC characteristics (VCC = 1.7V to 5.5V) table title modified. UFDFPN8 package specifications updated (see and M24128-BR part numbers added. 9 Generic part number corrected in I corrected in Table 14 CC0 Packages are ECOPACK® compliant. Revision history Changes and Section 2 ...

Page 34

... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 34/34 Please Read Carefully: © 2006 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com M24128, M24C64, M24C32 ...

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