LTC2446 LINER [Linear Technology], LTC2446 Datasheet
LTC2446
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LTC2446 Summary of contents
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... Protected by U.S. Patents, including 6140950, 6169506, 6208279, 6411242, 6639526 LTC2446 CS SDI ∆Σ ADC SDO SCK 24467 TA01 LTC2446/LTC2447 24-Bit High Speed U 2446/LTC2447 4-terminal switching enables and speeds as high as 8kHz. Through a RMS LTC2446 Speed vs RMS Noise 100 REF + – ...
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... Consult LTC Marketing for parts specified with wider operating temperature ranges (Notes 1, 2) Digital Output Voltage to GND ..... – 0. Operating Temperature Range + 0.3V) LTC2446C/LTC2447C .............................. 0°C to 70°C CC LTC2446I/LTC2447I ........................... – 40°C to 85°C + 0.3V) Storage Temperature Range ................. – 65°C to 125° 0.3V GND ...
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... CONDITIONS + Voltage – Voltage + Voltage – Voltage + – GND GND – REF = 5V, REF = GND 1.8MHz IN P-P LTC2446/LTC2447 MIN TYP MAX ● 24 ● ppm ppm of V ● 2 ● ppm of V ● ppm of V 0.2 ppm of V ● ...
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... LTC2446/LTC2447 U U DIGITAL I PUTS A D DIGITAL OUTPUTS operating temperature range, otherwise specifications are at T SYMBOL PARAMETER V High Level Input Voltage IH CS Low Level Input Voltage IL CS High Level Input Voltage IH SCK V Low Level Input Voltage IL SCK I Digital Input Current ...
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... SCK signal and outputs this on the SCK pin. A framing signal BUSY (Pin 2) goes low indicating data is being output. COM (Pin 7): The common negative input (IN single ended multiplexer configurations. The voltage on CH0-CH7 and COM pins can have any value between GND LTC2446/LTC2447 MIN TYP MAX ● ● ...
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... least 100mV. REF23 REF45 REF67 NC (Pins 24, 25, 26, 27): LTC2446 No Connect. These pins can either be tied to ground or left floating. MUXOUTP (Pin 24): LTC2447 Positive Input Channel Multiplexer Output. Used to drive the input to an external buffer/amplifier for the selected positive input signal (IN ADCINP (Pin 25): LTC2447 Positive ADC Input ...
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... AND CONTROL – REF + IN DIFFERENTIAL – 3RD ORDER IN ∆Σ MODULATOR DECIMATING FIR ADDRESS Figure 1. Functional Block Diagram = 20pF 24467 TA03 W U Figure 2. LTC2446/LTC2447 State Transition Diagram LTC2446/LTC2447 V CC INTERNAL OSCILLATOR F O (INT/EXT) SDI SCK SERIAL INTERFACE SDO CS 24467 F01 ...
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... These modes of operation are described in detail in the Serial Interface Timing Modes section. Ease of Use The LTC2446/LTC2447 data output has no latency, filter settling delay or redundant data associated with the conversion cycle while operating in the 1x mode. There is a one-to-one correspondence between the conversion and the output data ...
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... Outside this range, the converter indicates the overrange or the underrange condition using distinct output codes. MUXOUT/ADCIN There are two differences between the LTC2446 and the LTC2447. The first is the RMS noise performance. For a given OSR, the LTC2447 noise level is approximately √2 times lower (0 ...
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... For differential input voltages below –FS, the conversion result is clamped to the value corresponding to –FS – 1LSB. SERIAL INTERFACE PINS The LTC2446/LTC2447 transmit the conversion results and receive the start of conversion command through a – pins is maintained synchronous 3- or 4-wire interface. During the conver- ...
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... SDO pin on the falling edge of the serial clock. In the Internal SCK mode of operation, the SCK pin is an output and the LTC2446/LTC2447 create their own serial clock. In the External SCK mode of operation, the SCK pin is used as input. The internal or external SCK mode is selected by tying EXT (Pin 3) LOW for external SCK and HIGH for internal SCK ...
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... LTC2446/LTC2447 U U APPLICATIO S I FOR ATIO Table 3. Channel Selection for the LTC2446/LTC2447 MUX ADDRESS ODD/ SGL SIGN GLBL – – ...
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... U U APPLICATIO S I FOR ATIO Table 4. LTC2446/LTC2447 Speed/Resolution Selection OSR3 OSR2 OSR1 OSR0 TWOX ...
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... SERIAL INTERFACE TIMING MODES The LTC2446/LTC2447’ 4-wire interface is SPI and MICROWIRE compatible. This interface offers several flex- ible modes of operation. These include internal/external serial clock 4-wire I/O, single cycle conversion and autostart ...
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... EN SGL ODD GLBL A1 A0 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 “0” SIG MSB DATA OUTPUT Figure 4. External Serial Clock, Single Cycle Operation LTC2446/LTC2447 OSR3 OSR2 OSR1 OSR0 TWOX BIT 20 BIT 19 BIT 0 LSB Hi-Z ...
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... If a new channel is being programmed, the rising edge of CS must come after the 14th falling edge of SCK in order to store the data input sequence. 4.5V TO 5.5V 1µF = EXTERNAL OSCILLATOR INTERNAL OSCILLATOR LTC2446 29 + REFG 30 – REFG 11 + REF01 10 – REF01 . . ...
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... GND SGL ODD GLBL A1 A0 OSR3 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 SIG MSB DATA OUTPUT LTC2446/LTC2447 OSR2 OSR1 OSR0 TWOX DON'T CARE BIT 20 BIT 19 BIT 0 LSB CONVERSION 24467 F06 24467fa 17 ...
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... EOC = during the falling edge of EOC). The value of t 500ns pulled HIGH before time t remains in the sleep state. The conversion result is held in the internal static shift register. 4.5V TO 5.5V 1µ LTC2446 29 + REFG 30 – REFG 11 + USER SELECTABLE REF01 REFERENCES 10 – ...
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... CH7 BUSY 1,4,5,6,31,32,33 7 COM GND DON'T CARE BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 Hi-Z EOC “0” SIG MSB DATA OUTPUT CONVERSION LTC2446/LTC2447 = EXTERNAL OSCILLATOR = INTERNAL OSCILLATOR 4-WIRE SPI INTERFACE <t EOC(TEST) TEST EOC 6 DON'T CARE Hi-Z SLEEP CONVERSION 24467 F08 24467fa 19 ...
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... SCK. After the 32nd rising edge, SDO goes HIGH (EOC = 1) indicating a new conversion is in progress. SCK remains HIGH during the conversion. 4.5V TO 5.5V 1µ LTC2446 29 + REFG 30 – REFG 11 + USER SELECTABLE REF01 REFERENCES 10 – ...
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... Normal Mode Rejection and Antialiasing One of the advantages delta-sigma ADCs offer over con- ventional ADCs is on-chip digital filtering. Combined with a large oversampling ratio, the LTC2446/LTC2447 signifi- cantly simplify antialiasing filter requirements. The LTC2446/LTC2447’s speed/resolution is determined by the over sample ratio (OSR) of the on-chip digital filter. ...
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... RTDs or bridges, or universal data acquisition. Average Input Current The LTC2446 switches the input and reference to a 2pF capacitor at a frequency of 1.8MHz. A simplified equivalent circuit is shown in Figure 16. The sample capacitor for the LTC2447 is 4pF, and its average input current is externally buffered from the input source ...
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... SPI interface or by supplying an external conversion clock to the f pin. o Table 7 lists the properties of the LTC2446/LTC2447 with various combinations of oversample ratio and clock fre- 24467 F16 quency. Understanding these properties is the key to fine tuning the characteristics of the LTC2446/LTC2447 to the application ...
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... ADC will reject wideband input noise up to the modulator sample rate. The example on the following page shows how the noise rejection of the LTC2446/LTC2447 reduces the effective noise of an amplifier driving its input. Example amplifier (e.g. LT1219) driving the input of an LTC2446/LTC2447 has wideband noise of 33nV/√ ...
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... ADCs. MUX LTC2447 MUX 2 – 1 1/2 LT1368 3 + 0.1µF* (EXTERNAL AMPLIFIERS) CANCELLED – 7 1/2 LT1368 5 + 0.1µ LTC2446/LTC2447 + 0.3V. Using a positive CC SDI + REF SCK HIGH SPEED SDO ∆Σ ADC – REF CS *LT1368 REQUIRES 0.1µF OUTPUT COMPENSATION CAPACITOR 24467 F17 24467fa 25 ...
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... The reference terminals can also sense a resistive source with a resistance up to 500Ω located close to the LTC2446/ LTC2447, however parasitic capacitance must be kept to a minimum. If the sense point is more than 5cm from the ADC, then it should be buffered ...
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... DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE LTC2446/LTC2447 0.70 ± 0.05 PACKAGE OUTLINE 3.15 ± 0.10 0.435 ...
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... LTC2446/LTC2447 APPLICATIO S I FOR ATIO 5V V REF01 1µF – + 350Ω CH0 LOAD CELL FULL-SCALE OUTPUT = 10mV CH1 V REF01 1µF GND (18a) Full-Bridge, Voltage Sense 5V LT1790-3 V REF45 1µF 2850Ω CH5 GND 12.4k OMEGA 44018 LINEAR T2 T1 THERMISTOR COMPOSITE CH4 THERMISTOR 2850Ω ...