isp1181 NXP Semiconductors, isp1181 Datasheet
isp1181
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isp1181 Summary of contents
Page 1
... Full-speed Universal Serial Bus interface device Rev. 04 — 30 October 2001 1. General description The ISP1181 is a Universal Serial Bus (USB) interface device which complies with Universal Serial Bus Specification Rev. 1 provides full-speed USB communication capacity to microcontroller or microprocessor-based systems. The ISP1181 communicates with the system’s microcontroller or microprocessor through a high-speed general-purpose parallel interface. The ISP1181 supports fully autonomous, multi-confi ...
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... Heat sink very thin profile quad flat package; no leads; 48 terminals; body 7 9397 750 08938 Product data Router Modem Zip drive 7 0.85 mm Rev. 04 — 30 October 2001 ISP1181 Full-speed USB interface Version SOT362-1 SOT619-3 © Koninklijke Philips Electronics N.V. 2001. All rights reserved ...
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... MANAGEMENT CONTROLLER HANDLER UNIT INTEGRATED ENDPOINT RAM HANDLER INTERNAL I/O PIN 3.3 V SUPPLY SUPPLY 9 8 25, 36 ref WAKEUP GND V CC(3.3) to/from microcontroller 17 BUS_CONF0 18 BUS_CONF1 38 27, AD DATA1 to DATA9, BUS DATA10 to DATA15 INTERFACE CS, ALE, WR, RD INT ISP1181 MGS767 ...
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... EOT 10 DREQ 11 DACK 12 ISP1181DGG 13 TEST1 TEST2 14 INT 15 TEST3 16 BUS_CONF0 17 BUS_CONF1 18 DATA15 19 DATA14 20 DATA13 21 DATA12 22 DATA11 23 DATA10 24 MGL892 Rev. 04 — 30 October 2001 ISP1181 Full-speed USB interface 48 XTAL1 47 XTAL2 46 GND 45 CLKOUT 44 RESET ALE CC(3. GND 35 DATA1 34 DATA2 33 DATA3 ...
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... HVQFN48 AI AI Rev. 04 — 30 October 2001 ISP1181 Full-speed USB interface 25 DATA6 26 DATA5 27 DATA4 28 DATA3 29 DATA2 30 DATA1 31 GND 32 V CC(3. MBL316 Description supply voltage (3.3 or 5.0 V) voltage regulator ground supply regulated supply voltage (3 ...
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... DMA transfer to the ISP1181 DMA request output (4 mA; programmable polarity, see Table 22); signals to the DMA controller that the ISP1181 wants to start a DMA transfer DMA acknowledge input (programmable polarity, see Table 22); used by the DMA controller to signal the start of a DMA transfer requested by the ISP1181 test input ...
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... Rev. 04 — 30 October 2001 ISP1181 Full-speed USB interface Description bit 5 of D[15:0]; bi-directional data line (slew-rate controlled output, 4 mA) bit 4 of D[15:0]; bi-directional data line (slew-rate controlled output, 4 mA) bit 3 of D[15:0]; bi-directional data line (slew-rate controlled output, 4 mA) bit 2 of D[15:0]; bi-directional data line (slew-rate controlled output, 4 mA) bit 1 of D[15:0] ...
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... Rev. 04 — 30 October 2001 ISP1181 Full-speed USB interface Description ground supply crystal oscillator output (6 MHz); connect a fundamental parallel-resonant crystal; leave this pin open when using an external clock source on pin XTAL1 crystal oscillator input (6 MHz); connect a fundamental parallel-resonant crystal or an ...
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... USB endpoints. The type and FIFO size of each endpoint can be individually configured, depending on the required packet size. Isochronous and bulk endpoints are double-buffered for increased data throughput. The ISP1181 requires a single supply voltage of 3.3 or 5.0 V and has an internal 3.3 V voltage regulator for powering the analog USB transceiver. It supports bus-powered operation. ...
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... ISP1181 has been successfully enumerated (the device address is set), the LED indicator will remain permanently on. Upon each successful packet transfer (with ACK) to and from the ISP1181 the LED will blink off for 100 ms. During ‘suspend’ state the LED will remain off. ...
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... The ISP1181 has 16 endpoints: endpoint 0 (control IN and OUT) plus 14 configurable endpoints, which can be individually defined as interrupt/bulk/isochronous OUT. Each enabled endpoint has an associated FIFO, which can be accessed either via the parallel I/O interface or via DMA ...
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... The total amount of FIFO storage allocated to enabled endpoints must not exceed 2462 bytes. [2] IN: input for the USB host (ISP1181 transmits); OUT: output from the USB host (ISP1181 receives). The data flow direction is determined by bit EPDIR in the Endpoint Configuration Register. ...
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... OUT (64 byte fixed) 1023 double-buffered 1023-byte isochronous endpoint 16 16-byte interrupt OUT 16 16-byte interrupt IN 64 double-buffered 64-byte bulk OUT 64 double-buffered 64-byte bulk IN Rev. 04 — 30 October 2001 ISP1181 Full-speed USB interface Isochronous 16 bytes 32 bytes 48 bytes 64 bytes 96 bytes 128 bytes 160 bytes 192 bytes 256 bytes ...
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... IN endpoint to acknowledge success to the host. If there are errors in the endpoint configuration, the firmware must stall the control IN endpoint. When reset by hardware or via the USB bus, the ISP1181 disables all endpoints and clears all ECRs, except for the control endpoint which is fixed and always enabled. ...
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... I/O. The ISP1181 supports DMA transfer for all 14 configurable endpoints (see Only one endpoint at a time can be selected for DMA transfer. The DMA operation of the ISP1181 can be interleaved with normal I/O mode access to other endpoints. The following features are supported: • ...
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... It operates as a ‘fly-by’ DMA controller: the data is not stored in the DMA controller, but it is transferred between an I/O port and a memory address. A typical example of ISP1181 in 8237 compatible DMA mode is given in The 8237 has two control signals for each DMA channel: DRQ (DMA Request) and DACK (DMA Acknowledge) ...
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... The 8237 asserts DACK to inform the ISP1181 that it will start a DMA transfer. 7. The ISP1181 now places the byte or word to be transferred on the data bus lines, because its RD signal was asserted by the 8237. 8. The 8237 waits one DMA clock period and then de-asserts MEMW and IOR. This latches and stores the byte or word at the desired memory location ...
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... Philips Semiconductors In DACK-only mode the ISP1181 uses the DACK signal as data strobe. Input signals RD and WR are ignored. This mode is used in CPU systems that have a single address space for memory and I/O access. Such systems have no separate MEMW and MEMR signals: the RD and WR signals are also used as memory data strobes. ...
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... DMA operation after transferring the data bytes of this packet. When writing endpoint, a short packet transferred token will stop the DMA operation after all bytes have been transferred. If the number of bytes in the buffer is zero, ISP1181 will automatically send an empty packet. Table 10: EOT condition ...
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... All signals connected to ISP1181 must enter appropriate states to meet the b. All input pins of ISP1181 must have a CMOS logic 0 or logic 1 level the interrupt service routine the firmware must check the current status of the USB bus. When bit BUSTATUS in the Interrupt Register is logic 0, the USB bus has left ‘ ...
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... The SUSPEND output is active HIGH during ‘suspend’ state, making it suitable as a power switch control signal, e.g. for an external oscillator. Input pins of ISP1181 are pulled to ground via the pin buffers. Outputs are made three-state to prevent current flowing in the application. Bi-directional pins are made three-state and must be pulled to ground externally by the application ...
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... This prevents data corruption during power-up of external components. Figure 8 powered-off mode. The SUSPEND output is used to switch off power to the microcontroller and other external circuits during ‘suspend’ state. The ISP1181 is woken up via the USB bus (global resume the ring detection circuit on the telephone line. ...
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... Maximum 15 ms after starting the wake-up sequence the ISP1181 resumes its normal functionality case of a remote wake-up ISP1181 drives a K-state on the USB bus for 10 ms. 5. Following the de-assertion of output SUSPEND, the application restores itself and other system components to normal operating mode. ...
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... command code. Commands without a data phase are executed immediately. 2. Data phase (optional): when address bit the ISP1181 transfers the data on the bus to or from a register or endpoint FIFO. Multi-byte registers are accessed least significant byte/word first. ...
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... Endpoint Status Image Register endpoint 0 IN Endpoint Status Image Register n endpoint Endpoint 0 IN and OUT Error Code Register endpoint 0 OUT Error Code Register endpoint 0 IN Rev. 04 — 30 October 2001 ISP1181 Full-speed USB interface [1] Code (Hex) Transaction (00 bytes ...
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... Initialization commands Initialization commands are used during the enumeration process of the USB network. These commands are used to configure and enable the embedded endpoints. They also serve to set the USB assigned address of ISP1181 and to perform a device reset. 12.1.1 Write/Read Endpoint Configuration This command is used to access the Endpoint Confi ...
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... Write/Read Mode Register This command is used to access the ISP1181 Mode Register, which consists of 1 byte (bit allocation: see The Mode Register controls the DMA bus width, resume and suspend modes, interrupt activity and SoftConnect operation. It can be used to enable debug mode, where all errors and Not Acknowledge (NAK) conditions will generate an interrupt ...
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... Bus reset value: unchanged. - reserved SOFTCT A logic 1 enables SoftConnect (see ignored if EXTPUL = 1 in the Hardware Configuration Register (see Table 21). Bus reset value: unchanged. Table Rev. 04 — 30 October 2001 ISP1181 Full-speed USB interface DBGMOD reserved SOFTCT [1] [1] [1] 0 ...
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... Bus reset value: unchanged. EOTPOL Selects EOT signal polarity (0 = active LOW active HIGH). Bus reset value: unchanged. WKUPCS A logic 1 enables remote wake-up via a LOW level on input CS. Bus reset value: unchanged. Rev. 04 — 30 October 2001 ISP1181 Full-speed USB interface CKDIV[3: ...
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... IEP14 to IEP1 A logic 1 enables interrupts from the indicated endpoint. IEP0IN A logic 1 enables interrupts from the control IN endpoint. IEP0OUT A logic 1 enables interrupts from the control OUT endpoint. Rev. 04 — 30 October 2001 ISP1181 Full-speed USB interface …continued for details. Bus reset value: unchanged ...
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... Write/Read DMA Configuration This command defines the DMA configuration of ISP1181 and enables/disables DMA transfers. The command accesses the DMA Configuration Register, which consists of 2 bytes. The bit allocation is given in disabled), all other bits remain unchanged. Code (Hex): F0/F1 — write/read DMA Configuration Transaction — ...
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... R/W R DMACRL[7: R/W R/W R/W DMA Counter Register: bit description Symbol Description DMACRH[7:0] DMA Counter Register (high byte) DMACRL[7:0] DMA Counter Register (low byte) Rev. 04 — 30 October 2001 ISP1181 Full-speed USB interface …continued Section 12.1.6 for more details R/W R/W R R/W R/W R/W © Koninklijke Philips Electronics N.V. 2001. All rights reserved. ...
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... Philips Semiconductors 12.1.8 Reset Device This command resets the ISP1181 in the same way as an external hardware reset via input RESET. All registers are initialized to their ‘reset’ values. Code (Hex): F6 — reset the device Transaction — none 12.2 Data flow commands Data flow commands are used to manage the data transmission between the USB endpoints and the system microcontroller. Much of the data fl ...
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... D[15:0] 2 … … … 32. Reading the Endpoint Status Register will clear the interrupt bit set for the Rev. 04 — 30 October 2001 ISP1181 Full-speed USB interface Description data byte 2 … data byte N Description command code (00H to 1FH) packet length (lower byte) packet length (upper byte) ...
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... Setup packet. SETUPT A logic 1 indicates that the buffer contains a Setup packet. CPUBUF This bit indicates which buffer is currently selected for CPU access (0 = primary buffer secondary buffer). - reserved Rev. 04 — 30 October 2001 ISP1181 Full-speed USB interface 2 1 SETUPT CPUBUF reserved ...
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... A logic 1 indicates that the secondary endpoint buffer is full. EPFULL0 A logic 1 indicates that the primary endpoint buffer is full. DATA_PID This bit indicates the data PID of the present packet (0 = DATA0 PID DATA1 PID). Rev. 04 — 30 October 2001 ISP1181 Full-speed USB interface Section 9.5. Section 9.5. Table 34 ...
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... CPUBUF This bit indicates which buffer is currently selected for CPU access (0 = primary buffer secondary buffer). - reserved reserved ERROR[3: Rev. 04 — 30 October 2001 ISP1181 Full-speed USB interface …continued Section 9.5. Table 36 RTOK © Koninklijke Philips Electronics N.V. 2001. All rights reserved. ...
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... Unlock Device This command unlocks the ISP1181 from write-protection mode after a ‘resume’. In ‘suspend’ state all registers and FIFOs are write-protected to prevent data corruption by external devices during a ‘resume’. Register access for reading is not blocked. After waking up from ‘suspend’ state, the firmware must unlock the registers and FIFOs via this command, by writing the unlock code (AA37H) into the Lock Register (8-bit bus: lower byte fi ...
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... SFIRL[7: R/W R/W R/W Scratch Information Register: bit description Symbol Description - reserved; must be logic 0 SFIRH[6:0] Scratch Information Register (high byte) SFIRL[7:0] Scratch Information Register (low byte) Rev. 04 — 30 October 2001 ISP1181 Full-speed USB interface ...
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... D[7:0] - D[15:8] - data D[15: CHIPIDH[7:0] 81H CHIPIDL[7:0] XXH Rev. 04 — 30 October 2001 ISP1181 Full-speed USB interface SOFRH[2: Description command code (B4H) frame number (lower byte) frame number (upper byte) ...
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... EP4 EP3 EP2 PSOF SOF EOT Rev. 04 — 30 October 2001 ISP1181 Full-speed USB interface reserved reserved reserved EP9 EP8 EP7 EP1 ...
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... USB bus. RESUME A logic 1 indicates that a ‘resume’ state was detected. RESET A logic 1 indicates that a bus reset condition was detected, shows the interrupt logic of the ISP1181. Each of the indicated USB events 20). Rev. 04 — 30 October 2001 ISP1181 Full-speed USB interface Table 22) ...
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... Interrupt Register. SETUP and OUT token interrupts are generated after ISP1181 has acknowledged the associated data packet. In bulk transfer mode, the ISP1181 will issue interrupts for every ACK received for an OUT token or transmitted for an IN token. ...
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... V supply voltage for the internal logic and the USB transceiver. This voltage is available at pin V external pull-up resistor on USB connection D . See The ISP1181 can also be operated from a 3.0 to 3.6 V supply, as shown in In that case the internal voltage regulator is disabled and pin V connected to V ...
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... NOLAZY Fig 13. Oscillator and LazyClock logic. When ISP1181 enters ‘suspend’ state (by setting and clearing bit GOSUSP in the Mode Register), outputs SUSPEND and CLKOUT change state after approximately 2 ms delay. When NOLAZY = 0 the clock signal on output CLKOUT does not stop, but changes to the 115 kHz 10 % LazyClock frequency. When resuming from ‘ ...
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... Philips Semiconductors 16. Power-on reset The ISP1181 has an internal power-on reset (POR) circuit. Input pin RESET can be directly connected to V power-on and normally requires stabilize. The triggering voltage of the POR circuit is 2.0 V nominal. A POR is automatically generated when (1) Supply voltage ( 3.3 V), connected externally to pin RESET. ...
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... Product data Conditions V < > [1][2] I < 5. 8000 V. esd(max) Conditions Min with regulator 4.0 without regulator 3 Rev. 04 — 30 October 2001 ISP1181 Full-speed USB interface Min Max Unit 0.5 6 100 mA - 2000 V 60 150 C - 165 mW Typ Max Unit 5 ...
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... C CC amb 1.5 k pull-up on upstream port D (pin DP0) . CC(3. unless otherwise specified. GND amb Conditions I = rated drive rated drive OH Rev. 04 — 30 October 2001 ISP1181 Full-speed USB interface Min Typ Max [1] [2] 3.0 3.3 3 265 - - 50 202 Min ...
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... unless otherwise specified. amb Conditions V V I(D ) I(D ) includes V range 1 3. GND L pin to GND SoftConnect = ON steady-state drive ) both D and Rev. 04 — 30 October 2001 ISP1181 Full-speed USB interface Min Typ Max 0 0 0.8 2 0.3 2 ...
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... 10 [2][3] see Figure 16 see Figure 16 see Figure 17 see Figure 17 accepted as EOP; see Figure 16 rejected as EOP; see Figure 18 Rev. 04 — 30 October 2001 ISP1181 Full-speed USB interface Min Typ Max [ unless PU TERM Min Typ ...
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... N T PERIOD t JR2 t FST 3.3 V differential data lines 0 V Rev. 04 — 30 October 2001 ISP1181 Full-speed USB interface source EOP width: t EOPT receiver EOP width: t EOPR MGR776 t JR1 t JR2 V IH(min) MGR872 © Koninklijke Philips Electronics N.V. 2001. All rights reserved. MGR871 ...
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... HIGH logic LOW stop, not active (OFF) start, active (ON) valid logic level invalid logic level high-impedance (floating, three-state) Rev. 04 — 30 October 2001 ISP1181 Full-speed USB interface © Koninklijke Philips Electronics N.V. 2001. All rights reserved ...
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... Commands Acknowledge Setup, Clear Buffer, Validate Buffer and Write Endpoint Configuration require 180 ns to complete. 9397 750 08938 Product data Conditions 8-bit bus Min [ [2] [3] 90/180 reading 0 writing 0 Rev. 04 — 30 October 2001 ISP1181 Full-speed USB interface 16-bit bus Unit Max Min Max - 180 ...
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... Fig 20. Parallel interface write timing (I/O and 8237 compatible DMA). 9397 750 08938 Product data t RHAX t AVRL t SHDZ (1) t SHRL t WHAX (1) t SHWL t WHSH t WHDZ Rev. 04 — 30 October 2001 ISP1181 Full-speed USB interface MGS787 MGS789 © Koninklijke Philips Electronics N.V. 2001. All rights reserved ...
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... Product data LLAX t AVLL A0 Conditions Min Figure 22 and Figure 23) 100 90 90 and Figure 25) 100 90 90 data T cy(WC-WD) Rev. 04 — 30 October 2001 ISP1181 Full-speed USB interface D0 MGS790 8-bit bus 16-bit bus [1] [1] Max Min Max [2] - 205 - - 205 - - 205 - [2] - 205 ...
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... Fig 25. Read data + write command cycle timing. 9397 750 08938 Product data data command T cy(WD-WC) data T cy(WC-RD) T cy(RD-RD) data command T cy(RD-WC) Rev. 04 — 30 October 2001 ISP1181 Full-speed USB interface data (1) MGT025 data MGT023 data (1) MGT024 © Koninklijke Philips Electronics N.V. 2001. All rights reserved ...
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... Fig 26. DMA timing in 8237 compatible mode. 9397 750 08938 Product data Conditions Min EOT on; 22 DACK on; RD/WR LOW - - T cy(DREQ) t ASRP Rev. 04 — 30 October 2001 ISP1181 Full-speed USB interface 8-bit bus 16-bit bus Max Min Max 180 - 180 - ...
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... Product data t ASRP t ASAP t ASDV t ASAP t ASRP t DVAP t RSIH t ASRP t IHAP (1) t RLIS t EOT t WLIS (3) Rev. 04 — 30 October 2001 ISP1181 Full-speed USB interface t APRS t APDZ MGS793 t APRS t APDZ MGS794 MGS795 © Koninklijke Philips Electronics N.V. 2001. All rights reserved ...
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... DREQ DACK RD/WR Fig 30. Burst mode DMA timing. 9397 750 08938 Product data Conditions Min EOT on; 22 DACK on; RD/WR LOW - - - t RSIH t ILRP t IHIL Rev. 04 — 30 October 2001 ISP1181 Full-speed USB interface 8-bit bus 16-bit bus Max Min Max - 180 - - ...
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... The EOT condition is considered valid if DACK, RD/WR and EOT are all active (= LOW). Fig 31. EOT timing in burst mode DMA. 9397 750 08938 Product data t ISRP t RLIS t WLIS (1) t EOT Rev. 04 — 30 October 2001 ISP1181 Full-speed USB interface MGS797 © Koninklijke Philips Electronics N.V. 2001. All rights reserved ...
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... DATA14 D DATA15 D+ ISP1181 A0 ALE XTAL1 XTAL2 INT SUSPEND WAKEUP DREQ GL DACK EOT BUS_CONF1 BUS_CONF0 Rev. 04 — 30 October 2001 ISP1181 Full-speed USB interface V CC LINK LED 0.1 0 USB upstream connector 330 6 MHz MGS769 © Koninklijke Philips Electronics N.V. 2001. All rights reserved. ...
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... BUS_CONF1 BUS_CONF0 D15 D14 D13 D12 D11 16 BIT D10 DMA PORT Rev. 04 — 30 October 2001 ISP1181 Full-speed USB interface V CC LINK LED V reg(3. RESET 0.1 0 USB upstream connector V BUS XTAL1 ...
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... CS7 when external address space for the associated area is accessed. The ISP1181 can be mapped to any address area, allowing easy interfacing when the ISP1181 is the only device in that area the example circuit for bus configuration mode 0 (see output CS7 of the H8S/2357 can be directly connected to input CS of the ISP1181. ...
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... Philips Semiconductors 20.2.4 Using H8S2357 I/O Ports In the interface circuit of general purpose output port. This pin drives the ISP1181’s WAKEUP input to generate a remote wake-up. The H8S/2357 has 3 registers to configure port 1: Port 1 Data Direction Register (P1DDR), Port 1 Data Register (P1DR) and Port 1 Register (PORT1). Only registers P1DDR and P1DR must be confi ...
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... 2 scale (1) ( 0.28 0.2 0.2 12.6 6.2 8.3 0.5 0.17 0.1 0.1 12.4 6.0 7.9 REFERENCES JEDEC EIAJ MO-153 Rev. 04 — 30 October 2001 ISP1181 Full-speed USB interface detail 0.8 0.50 0.8 1 0.25 0.08 0.1 0.4 0.35 0.4 EUROPEAN ISSUE DATE PROJECTION 95-02-10 99-12-27 © Koninklijke Philips Electronics N.V. 2001. All rights reserved. ...
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... 2 scale 6.85 5.25 7.15 6.85 5.25 0.5 5.5 6.65 4.95 6.85 6.65 4.95 REFERENCES JEDEC EIAJ MO-220 Rev. 04 — 30 October 2001 ISP1181 Full-speed USB interface detail 0.50 5.5 0.2 0.1 0.08 0.1 0.30 EUROPEAN ISSUE DATE PROJECTION 01-08-31 01-09-07 © Koninklijke Philips Electronics N.V. 2001. All rights reserved. ...
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... For packages with leads on four sides, the footprint must be placed angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. 9397 750 08938 Product data Rev. 04 — 30 October 2001 ISP1181 Full-speed USB interface © Koninklijke Philips Electronics N.V. 2001. All rights reserved ...
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... Product data Suitability of surface mount IC packages for wave and reflow soldering methods [3] , SO, SOJ Rev. 04 — 30 October 2001 ISP1181 Full-speed USB interface Soldering method Wave Reflow not suitable suitable [2] ...
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... Revision history Rev Date CPCN Description 04 20011030 - Product data; fourth version. Supersedes ISP1181-03 of June 11th, 2001 (9397 750 08504). Modifications: • Added new USB basic speed logo to indicate ISP1181 as a USB-IF certified product. • In • In • In • Section SOT619-3. ...
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... GoodLink — trademark of Koninklijke Philips Electronics N.V. OnNow — trademark of Microsoft Corp. SoftConnect — trademark of Koninklijke Philips Electronics N.V. Zip — registered trademark of Iomega Corp. Rev. 04 — 30 October 2001 ISP1181 Full-speed USB interface Fax: + 24825 © Koninklijke Philips Electronics N.V. 2001. All rights reserved ...
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... Timing symbols 19.2 Parallel I/O timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 19.3 Access cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . 55 19.4 DMA timing: single-cycle mode . . . . . . . . . . . . . . . . 57 19.5 DMA timing: burst mode . . . . . . . . . . . . . . . . . . . . . . 59 20 Application information . . . . . . . . . . . . . . . . . . . . . . . 61 20.1 Typical interface circuits . . . . . . . . . . . . . . . . . . . . . . 61 20.2 Interfacing ISP1181 with an H8S/2357 microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 20.2.1 Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 20.2.2 Address mapping in H8S/2357 . . . . . . . . . . . . . . . . . 63 20.2.3 Using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 20.2.4 Using H8S2357 I/O Ports . . . . . . . . . . . . . . . . . . . . . 64 21 Test information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 22 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 23 Soldering ...