IDTCSPUA877 Integrated Device Technology, IDTCSPUA877 Datasheet

IDTCSPUA877

Manufacturer Part Number

IDTCSPUA877

Description

1.8v Phase Locked Loop Differential 1 10 Sdram Clock Driver

Manufacturer

Integrated Device Technology

Datasheet

1.IDTCSPUA877.pdf (13 pages)

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Part Number:

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IDT

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The IDT logo is a registered trademark of Integrated Device Technology, Inc.

FEATURES:

• 1 to 10 differential clock distribution

• Optimized for clock distribution in DDR2 (Double Data Rate)

• Operating frequency: 125MHz to 410MHz

• Stabilization time: <6us

• Very low skew: ≤ ≤ ≤ ≤ ≤ 40ps

• Very low jitter: ≤ ≤ ≤ ≤ ≤ 40ps

• 1.8V AV

• CMOS control signal input

• Test mode enables buffers while disabling PLL

• Low current power-down mode

• Tolerant of Spread Spectrum input clock

• Available in VFBGA package

NOTE:

The Logic Detect (LD) powers down the device when a logic LOW is applied to both CLK and CLK.

COMMERCIAL TEMPERATURE RANGE

APPLICATIONS:

• Meets or exceeds JEDEC standard CUA877 for registered DDR2

• Along with SSTUA32864/66, DDR2 register, provides complete

FUNCTIONAL BLOCK DIAGRAM

IDTCSPUA877

1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER

SDRAM applications

clock driver

solution for DDR2 DIMMs

2006 Integrated Device Technology, Inc.

and 1.8V V

DDQ

10KΩ - 100KΩ

FBIN

CLK

1.8V PHASE LOCKED LOOP

DIFFERENTIAL 1:10 SDRAM

CLOCK DRIVER

POWER

LOGIC

DOWN

MODE

TEST

PLL

AND

DESCRIPTION:

to distribute one differential clock input pair(CLK, CLK ) to 10 differential

output pairs (Y

(FBOUT, FBOUT). External feedback pins (FBIN, FBIN) for synchronization

of the outputs to the input reference is provided. OE, OS, and A

power-down and test mode logic. When A

off and bypassed for test mode purposes. When the differential clock inputs

(CLK, CLK) are both at logic low, this device will enter a low power-down mode.

In this mode, the receivers are disabled, the PLL is turned off, and the output

clock drivers are disabled, resulting in a clock driver current consumption of less

than 500μA.

for very low phase error, skew, and jitter, while maintaining frequency and duty

cycle over the operating voltage and temperature range. The CSPUA877 ,

designed for use in both module assemblies and system motherboard based

solutions, provides an optimum high-performance clock source.

+70°C). See Ordering Information for details.

The CSPUA877 is a PLL based clock driver that acts as a zero delay buffer

The CSPUA877 requires no external components and has been optimised

The CSPUA877 is available in Commercial Temperature Range (0°C to

LD, OS, or OE

LD or OE

PLL BYPASS

[0:9]

, Y

[0:9]

) and one differential pair of feedback clock output

COMMERCIAL TEMPERATURE RANGE

FBOUT

VDD

is grounded, the PLL is turned

IDTCSPUA877

OCTOBER 2006

VDD

DSC-6518/9

control the

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