IDTCSPT855 Integrated Device Technology, IDTCSPT855 Datasheet

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IDTCSPT855

Manufacturer Part Number
IDTCSPT855
Description
2.5v Phase Locked Loop Clock Driver
Manufacturer
Integrated Device Technology
Datasheet

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Part Number:
IDTCSPT855PGG
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IDT
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629
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IDTCSPT855PGGI
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IDTCSPT855PGGI
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FEATURES:
• PLL clock driver for DDR (Double Data Rate) synchronous
• Spread spectrum clock compatible
• Operating frequency: 60MHz to 220MHz
• Low jitter (cycle-to-cycle): ±50ps
• Distributes one differential clock input to four differential clock
• Enters low power mode and 3-state outputs when input CLK
• Operates from a 2.5V supply
• Consumes <200μ μ μ μ μ A quiescent current
• External feedback pins (FBIN, FBIN) are used to synchronize
• Available in TSSOP package
APPLICATIONS:
• For all DDR1 speeds: PC1600 (DDR200), PC2100 (DDR266),
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
FUNCTIONAL BLOCK DIAGRAM
IDTCSPT855
2.5V PLL CLOCK DRIVER
c
DRAM applications
outputs
signal is less than 20MHz or PWRDWN is low
outputs to input clocks
PC2700 (DDR333), PC3200 (DDR400)
2005 Integrated Device Technology, Inc.
PWRDWN
FBIN
FBIN
CLK
CLK
AV
DD
6
7
23
22
24
9
2.5V PHASE LOCKED LOOP
CLOCK DRIVER
POWERDOWN
AND TEST
LOGIC
PLL
1
DESCRIPTION:
that distributes one differential clock input pair(CLK, CLK ) to four differential
output pairs (Y
(FBOUT, FBOUT). When PWRDWN is high, the outputs switch in phase and
frequency with CLK. When PWRDWN is low, all outputs are disabled to a high-
impedance state (3-state), and the PLL is shut down (low-power mode). The
device also enters this low-power mode when the input frequency falls below
a suggested detection frequency that is below 20MHz (typical 10MHz). An input
frequency detection circuit detects the low-frequency condition, and after
applying a >20MHz input signal, this detection circuit reactivates the PLL and
enables the outputs.
purposes. The CSPT855 is also able to track spread spectrum clocking for
reduced EMI.
to achieve phase-lock of the PLL. This stabilization time is required following
power up.
The CSPT855 is a high-performance, low-skew, low-jitter zero delay buffer
When AV
Since the CSPT855 is based on PLL circuitry, it requires a stabilization time
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
DD
[0:3]
is tied to GND, the PLL is turned off and bypassed for test
, Y
[0:3]
) and one differential pair of feedback clock outputs
12
13
17
16
26
27
19
20
3
2
Y0
Y0
Y1
Y1
Y2
Y2
Y3
Y3
FBOUT
FBOUT
AUGUST 2005
IDTCSPT855
DSC-6203/11

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IDTCSPT855 Summary of contents

Page 1

... The CSPT855 is also able to track spread spectrum clocking for reduced EMI. Since the CSPT855 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up. POWERDOWN AND TEST LOGIC PLL 1 IDTCSPT855 , Y ) and one differential pair of feedback clock outputs [0: ...

Page 2

... IDTCSPT855 2.5V PLL CLOCK DRIVER PIN CONFIGURATION 1 GND DDQ 5 GND CLK 6 7 CLK 8 V DDQ AGND V 11 DDQ GND 14 TSSOP TOP VIEW PIN DESCRIPTION Pin Name Pin Number AGND CLK, CLK ...

Page 3

... IDTCSPT855 2.5V PLL CLOCK DRIVER FUNCTION TABLE (1) INPUTS PWRDWN AV CLK DD GND H L GND 2.5V (nom 2.5V (nom 2.5V (nom) X <20MHz NOTES HIGH Voltage Level L = LOW Voltage Level Z = High-Impedance OFF-State X = Don't Care 2. Typically 10MHz. RECOMMENDED OPERATING CONDITIONS Symbol AV V Supply Voltage ...

Page 4

... IDTCSPT855 2.5V PLL CLOCK DRIVER DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Commercial 0°C to +70°C; Industrial Symbol Parameter V Input Voltage (All Inputs HIGH-Level Output Voltage OH V LOW-Level Output Voltage OL I HIGH-Level Output Current OH I LOW-Level Output Current ...

Page 5

... IDTCSPT855 2.5V PLL CLOCK DRIVER SWITCHING CHARACTERISTICS Symbol Description PLH (2) t LOW to HIGH Level Propagation Delay Time PHL (2) t HIGH to LOW Level Propagation Delay Time JIT(PER) (3) t Jitter (period), see figure 6 JIT(CC) (3) t Jitter (cycle-to-cycle), see figure 2 JIT(HPER) (3) t Half-Period Jitter, see figure 7 ...

Page 6

... IDTCSPT855 2.5V PLL CLOCK DRIVER TEST CIRCUIT AND SWITCHING WAVEFORMS 60Ω 60Ω CSPT855 NOTE GND TT Yx, FBOUT Yx, FBOUT COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES R = 10Ω 14pF 10Ω 14pF Figure 1. Output Load Test Circuit t t cycle n ...

Page 7

... IDTCSPT855 2.5V PLL CLOCK DRIVER TEST CIRCUIT AND SWITCHING WAVEFORMS CLK CLK FBIN FBIN CLK CLK FBIN FBIN t D(Ø Yx, FBOUT Yx, FBOUT COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES t (Ø)n ∑ (Ø)n (Ø Figure 3. Static Phase Offset t (Ø D(Ø) D(Ø ...

Page 8

... IDTCSPT855 2.5V PLL CLOCK DRIVER TEST CIRCUIT AND SWITCHING WAVEFORMS Yx, FBOUT Yx, FBOUT Yx, FBOUT Yx, FBOUT Yx, FBOUT Yx, FBOUT Yx, FBOUT Yx, FBOUT COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES t cycle jit(per) = cycle Figure 6. Period jitter t t half period n+1 half period jit(hper) = ...

Page 9

... IDTCSPT855 2.5V PLL CLOCK DRIVER TEST CIRCUIT AND SWITCHING WAVEFORMS 80% C lock Inputs and O utputs 20% COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES (I Figure 8. Input and Output Slew Rates ...

Page 10

... IDTCSPT855 2.5V PLL CLOCK DRIVER ORDERING INFORMATION XXXXX XX IDTCSPT Package Device Type CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES X Process Blank I PG PGG 855 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 10 0°C to +70°C (Commercial) -40° ...

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