IDT72V281 IDT [Integrated Device Technology], IDT72V281 Datasheet
IDT72V281
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IDT72V281 Summary of contents
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... Slim Thin Quad Flat Pack (STQFP) High-performance submicron CMOS technology Industrial Temperature Range (-40° 85°C) is available The IDT72V281/72V291 are exceptionally deep, high speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write controls. These FIFOs offer numerous improvements over previous SuperSync ...
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... IDT72V281/72V291 SuperSync FIFOs are particularly appropriate for network, video, telecommu- nications, data communications and other applications that need to buffer large amounts of data. The input port is controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data is written into the FIFO on every rising edge of WCLK when WEN is asserted ...
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... Once in the power down state, the standby supply current consumption is minimized. Initiating any operation (by activating control inputs) will immediately take the device out of the power down state. The IDT72V281/72V291 are fabricated using IDT’s high speed submi- cron CMOS technology. PARTIAL RESET (PRS) MASTER RESET (MRS) ...
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... IDT72V281/72V291 Symbol Name D –D Data Inputs 0 8 MRS Master Reset PRS Partial Reset RT Retransmit FWFT/SI First Word Fall Through/Serial In WCLK Write Clock WEN Write Enable RCLK Read Clock REN Read Enable OE Output Enable SEN Serial Enable LD Load DC Don't Care FF/IR Full Flag/ ...
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... Supply Voltage(Com’l & Ind’l) 0 Input High Voltage (Com’l & Ind’l) 2.0 Input Low Voltage (Com’l & Ind’l) — Operating Temperature 0 Commercial Operating Temperature -40 Industrial IDT72V281L IDT72V291L Com’l & Ind’l ( 10, 15 CLK Min. Max. –1 1 –10 10 2.4 — ...
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... GND to 3.0V 3ns 1.5V 1.5V See Figure 2 6 Com’l & Ind’l (2) Commercial IDT72V281L15 IDT72V281L20 IDT72V291L15 IDT72V291L20 Min. Max. Min. Max. — 66.7 — — 20 — 6 — 8 — 6 — 8 — 4 — ...
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... When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting further write operations reads are performed after a reset, IR will go HIGH after D writes to the FIFO 65,537 writes for the IDT72V281 and 131,073 writes for the IDT72V291, respectively. Note that the additional word in FWFT mode is due to the capacity of the memory plus output register ...
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... IDT72V281/72V291 In addition to loading offset values into the FIFO, it also possible to read the current offset values only possible to read offset values via parallel read. Figure 4, Programmable Flag Offset Programming Sequence, summa- rizes the control pins and sequence for both serial and parallel programming modes ...
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... IDT72V281/72V291 72V281 (65,536 x 9›BIT EMPTY OFFSET (LSB) REGISTER DEFAULT VALUE 7FH LOW at Master Reset FFH HIGH at Master Reset 8 7 EMPTY OFFSET (MSB) REGISTER DEFAULT VALUE 00H LOW at Master Reset 03H HIGH at Master Reset 8 7 FULL OFFSET (LSB) REGISTER ...
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... WCLK edges plus t rising RCLK edges plus t The act of reading the offset registers employs a dedicated read offset register pointer. The contents of the offset registers can be read on the Q pins when LD is set LOW and REN is set LOW. For the IDT72V281 ...
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... words should have been written into the FIFO between Reset (Master or Partial) and the time of Retransmit setup 65,536 for the IDT72V281 and D = 131,072 for the IDT72V291 in IDT Standard mode. In FWFT mode 65,537 for the IDT72V281 and D = 131,073 for the IDT72V291 ...
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... IDT72V281/72V291 DATA Data inputs for 9-bit wide data. MRS) MRS MRS MRS MASTER RESET (MRS A Master Reset is accomplished whenever the MRS input is taken to a LOW state. This operation sets the internal read and write pointers to the first location of the RAM array. PAE will go LOW, PAF will go HIGH, and HF will go HIGH ...
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... IR goes HIGH, inhibiting further write operations reads are performed after a reset (either MRS or PRS), IR will go HIGH after D writes to the FIFO (D = 65,537 for the IDT72V281 and after the valid WCLK cycle. 131,073 for the IDT72V291) See Figure 9, Write Timing (FWFT Mode), for the relevant timing information ...
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... PAF will go LOW after ( words are written to the FIFO. The PAF will go LOW after (65,536-m) writes for the IDT72V281 and (131,072-m) writes for the IDT72V291. The offset “m” is the full offset value. The default setting for this value is stated in the footnote of Table 1 ...
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... IDT72V281/72V291 MRS REN WEN t FWFT FWFT/ SEN EF/OR FF/IR PAE PAF COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE RSS t RSS t RSS t RSS t RSS If FWFT = HIGH HIGH t RSF If FWFT = LOW LOW t If FWFT = LOW HIGH RSF If FWFT = HIGH LOW t RSF t RSF t RSF Figure 5 ...
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... IDT72V281/72V291 PRS REN WEN RT SEN EF/OR FF/IR PAE PAF COCOMMCOMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE RSS t RSS t RSS t RSS t RSF t RSF t RSF t RSF t RSF Figure 6. Partial Reset Timing 16 t RSR t RSR If FWFT = HIGH HIGH If FWFT = LOW LOW If FWFT = LOW HIGH If FWFT = HIGH LOW ...
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... IDT72V281/72V291 NO WRITE WCLK 1 (1) t SKEW1 WEN RCLK t t ENS ENH REN DATA IN OUTPUT REGISTER NOTES: is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go high (after one WCLK cycle pus ...
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... SKEW2 , then the PAE deassertion may be delayed one extra RCLK cycle. t SKEW2 HIGH LOW PAE offset PAF offset and D = maximum FIFO depth 65,537 for the IDT72V281 and 131,073 for the IDT72V291. 6. First data word latency: 60ns + t + 2*T . REF RCLK ...
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... RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH after one WCLK cycle plus SKEW2 , then the PAF deassertion may be delayed one extra WCLK cycle. t SKEW2 HIGH PAE Offset PAF offset and D = maximum FIFO depth 65,537 for the IDT72V281 and 131,073 for the IDT72V291. ( ...
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... FIFO after Master Reset more than may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure 65,536 for the IDT72V281 and 131,072 for the IDT72V291 goes HIGH at 60ns + 1 RCLK cycle + t . ...
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... OR goes LOW at 60ns + 2 RCLK cycles + t . REF WCLK t ENS SEN t LDS BIT 0 SI NOTE for the IDT72V281 and for the IDT72V291. Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes) COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE 1 W x+1 t SKEW2 ENH t REF t ...
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... CLKH CLKL RCLK t LDS LD t ENS REN DATA IN OUTPUT REGISTER NOTE LOW Figure 16. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes) for the IDT72V281 t CLK t CLKH t CLKL RCLK t t LDS LDH ENS ENH REN ...
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... REN NOTES: 1. For IDT Standard mode maximum FIFO depth 65,536 for the IDT72V281 and 131,072 for the IDT72V291. 2. For FWFT mode maximum FIFO depth 65,537 for the IDT72V281 and 131,073 for the IDT72V291. Figure 20. Half-Full Flag Timing (IDT Standard and FWFT Modes) ...
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... Figure 21. Block Diagram of 65,536 x 18 and 131,072 x 18 Width Expansion DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY) The IDT72V281 can easily be adapted to applications requiring depths greater than 65,536 and 131,072 for the IDT72V291 with a 9-bit bus width. In FWFT mode, the FIFOs can be connected in series (the data outputs of one FIFO connected to the data inputs of the next) with no external logic necessary ...
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... IDT72V281/72V291 FWFT/SI FWFT/SI WRITE CLOCK WCLK WRITE ENABLE WEN IDT INPUT READY IR 72V281 72V291 n DATA IN Dn Figure 22. Block Diagram of 131,072 x 9 and 262,144 x 9 Depth Expansion For a full expansion configuration, the amount of time it takes for IR of the first FIFO in the chain to go LOW after a word has been read from the last FIFO is the sum of the delays for each individual FIFO: (N – ...
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IDT XXXXX X XX Device Type Power Speed NOTE: 1. Industrial temperature range product for the 15ns speed grade is available as a standard device. 04/24/2001 pgs and 26. 2975 Stender Way Santa Clara, CA 95054 SuperSyncFIFO ...