IDT72801 Integrated Device Technology, Inc., IDT72801 Datasheet
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IDT72801
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IDT72801 Summary of contents
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... FEATURES: • • • • • The IDT72801 is equivalent to two IDT72201 256 x 9 FIFOs • • • • • The IDT72811 is equivalent to two IDT72211 512 x 9 FIFOs • • • • • The IDT72821 is equivalent to two IDT72221 1,024 x 9 FIFOs • • • • • ...
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... IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL PIN CONFIGURATION WENA2/LDA WCLKA WENA1 RSA TQFP (PN64-1, order code: PF) STQFP (PP64-1, order code: TF) TOP VIEW 2 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 48 QB0 FFB 47 EFB 46 OEB 45 RENB2 44 RCLKB ...
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... IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL PIN DESCRIPTIONS The IDT72801/72811/72821/72831/72841/72851s two FIFOs, referred to as FIFO A and FIFO B, are identical in every respect. The following Symbol Name I/O DA0-DA8 A Data Inputs I DB0-DB8 B Data Inputs I RSA ...
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... IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL ABSOLUTE MAXIMUM RATINGS Symbol Rating Terminal Voltage with V TERM Respect to GND Temperature T Storage STG Current I DC Output OUT NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device ...
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... IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL ELECTRICAL CHARACTERISTICS (Commercial ± 10 0°C to +70°C; Industrial Symbol Parameter f Clock Cycle Frequency S t Data Access Time A t Clock Cycle Time CLK t Clock High Time CLKH ...
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... IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL SIGNAL DESCRIPTIONS FIFO A and FIFO B are identical in every respect. The following description explains the interaction of input and output signals for FIFO A. The correspond- ing signal names for FIFO B are provided in parentheses. ...
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... Full Flag (FFA, FFB) — FFA (FFB) will go LOW, inhibiting further write operations, when Array A (B) is full reads are performed after reset, FFA (FFB) will go LOW after 256 writes to the IDT72801's FIFO A (B); 512 writes to the IDT72811's FIFO A (B); 1,024 writes to the IDT72821's FIFO A (B); 2,048 writes to the IDT72831's FIFO A (B) ...
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... LOW when the amount of data in Array A (B) reaches the almost-full condition reads are performed after Reset, PAFA (PAFB) will go LOW after (256-m) writes to the IDT72801's FIFO A (B); (512-m) writes to the IDT72811's FIFO A (B); (1,024-m) writes to the IDT72821's FIFO A (B); (2,048-m) writes to the IDT72831's FIFO A (B) ...
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... IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL RSA (RSB) RENA1, RENA2 (RENB1, RENB2) WENA1 (WENB1) (1) WENA2/LDA (WENB2/LDB) EFA, PAEA (EFB, PAEB) FFA, PAFA (FFB, PAFB ( NOTES: 1. Holding WENA2/LDA (WENB2/LDB) HIGH during reset will make the pin act as a second write enable pin. Holding WENA2/LDA (WENB2/LDB) LOW during reset will make the pin act as a load enable for the programmable flag offset registers ...
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... IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL RCLKA (RCLKB) t ENS RENA1, RENA2 (RENB1, RENB2) EFA (EFB ( OEA (OEB) WCLKA (WCLKB) WENA1 (WENB1) WENA2 (WENB2) NOTE: is the minimum time between a rising WCLKA (WCLKB) edge and a rising RCLKA (RCLKB) edge for EFA (EFB) to change during the current clock cycle. If the time 1 ...
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... IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL WRITE WCLKA (WCLKB) t SKEW1 ( FFA (FFB) WENA1 (WENB1) WENA2 (WENB2) (If Applicable) RCLKA (RCLKB) t ENH t ENS RENA1 (RENB2) OEA LOW (OEB DATA IN OUTPUT REGISTER ( NOTE: 1. Only one of the two write enable inputs, WEN1 or WEN2, needs to go inactive to inhibit writes to the FIFO. ...
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... NOTES PAF offset. 2. (256-m) words for the IDT72801; (512-m) words the IDT72811; (1,024-m) words for the IDT72821; (2,048-m) words for the IDT72831; (4,096-m) words for the IDT72841; or (8,192-m) words for the IDT72851. is the minimum time between a rising RCLKA (RCLKB) edge and a rising WCLKA (WCLKB) edge for PAFA (PAFB) to change during that clock cycle. If the time between the 3 ...
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... IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO DUAL 256 x 9, DUAL 512 x 9, DUAL DUAL DUAL DUAL CLK WCLKA (WCLKB) LDA (LDB) WENA1 (WENB1 ( PAE OFFSET (LSB) t CLK t CLKH RCLKA (RCLKB) t LDA (LDB) t ENS RENA1, RENA2 (RENB1, RENB2 DATA IN OUTPUT REGISTER ( CLKL t t ENS ...
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... WRITE ENABLE/LOAD WENA2/LDA FFA FULL FLAG FFB Figure 15. Block diagram of the two FIFOs contained in one IDT72801/72811/ 72821/72831/72841/72851 configured for an 18-bit width-expansion TM can be grounded (see Figure 14). In this configuration, the Write Enable 2/ Load WENA2/LDA (WENB2/LDB) pin is set LOW at Reset so that the pin operates as a control to load and read the programmable flag offsets ...
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... When writing from the bus to the FIFO, control logic sorts the intermixed Processor Clock Address Control Data 9 RAM 9 BIDIRECTIONAL CONFIGURATION The two FIFOs of the IDT72801/72811/72821/72831/72841/72851 can be used to buffer data flow in two directions. In the example that follows, a Processor Clock Address Control Data 9 RAM 9 ...
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... DEPTH EXPANSION — IDT72801/72811/72821/72831/72841/72851 can be adapted to applications that require greater than 256/512/1,024/ 2,048/4,096/8,192 words. The existence of double enable pins on the read and write ports allow depth expansion. The Write Enable 2/Load (WENA2, WENB2) pins are used as a second write enables in a depth expansion configuration, thus the Programmable flags are set to the default values ...