IDT71V65703 Integrated Device Technology, IDT71V65703 Datasheet

IDT71V65703

Manufacturer Part Number

IDT71V65703

Description

256k X 36, 512k X 18 3.3v Synchronous Zbt Srams

Manufacturer

Integrated Device Technology

Datasheet

1.IDT71V65703.pdf (26 pages)

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(9 Megabit) synchronous SRAMs organized as 256K x 36 / 512K x 18.

They are designed to eliminate dead bus cycles when turning the bus

around between reads and writes, or writes and reads. Thus they have

been given the name ZBT

R/W

CLK

I/O

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.

CEN

ADV/LD

LBO

-A

The IDT71V65703/5903 are 3.3V high-speed 9,437,184-bit

Address and control signals are applied to the SRAM during one clock

256K x 36, 512K x 18 memory configurations

Supports high performance system speed - 100 MHz

(7.5 ns Clock-to-Data Access)

ZBT

cycles

Internally synchronized output buffer enable eliminates the

need to control OE

Single R/W (READ/WRITE) control pin

4-word burst capability (Interleaved or linear)

Individual byte write (BW

Three chip enables for simple depth expansion

3.3V power supply (±5%)

3.3V (±5%) I/O Supply (V

Power down controlled by ZZ input

Packaged in a JEDEC standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch

ball grid array (fBGA).

-I/O

, CE

, V

, BW

DDQ

, I/O

, CE

, BW

Feature - No dead cycles between write and read

-I/O

, BW

, or Zero Bus Turnaround.

Chip Enables

Output Enable

Read/Write Signal

Clock Enable

Individual Byte Write Selects

Clock

Linear/Interleaved Burst Order

Sleep Mode

Data Input/Output

Core Power, I/O Power

Ground

Address Inputs

Advance Burst Address/Load New Address

DDQ

- BW

)

) control (May tie active)

256K x 36, 512K x 18

3.3V Synchronous ZBT™ SRAMs

3.3V I/O, Burst Counter

Flow-Through Outputs

cycle, and on the next clock cycle the associated data cycle occurs, be it

read or write.

registers. The outputs are flow-through (no output data register). Output

enable is the only asynchronous signal and can be used to disable the

outputs at any given time.

to be suspended as long as necessary. All synchronous inputs are ignored when

CEN is high and the internal device registers will hold their previous values.

user to deselect the device when desired. If any one of these three is not

asserted when ADV/LD is low, no new memory operation can be initiated.

However, any pending data transfers (reads or writes) will be completed.

The data bus will tri-state one cycle after the chip is deselected or a write

is initiated.

mode, the IDT71V65703/5903 can provide four cycles of data for a single

address presented to the SRAM. The order of the burst sequence is

defined by the LBO input pin. The LBO pin selects between linear and

interleaved burst sequence. The ADV/LD signal is used to load a new

external address (ADV/LD = LOW) or increment the internal burst counter

(ADV/LD = HIGH).

CMOS process and are packaged in a JEDEC Standard 14mm x 20mm 100-

pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) and a 165

fine pitch ball grid array (fBGA).

The IDT71V65703/5903 contain address, data-in and control signal

A Clock Enable (CEN) pin allows operation of the IDT71V65703/5903

There are three chip enable pins (CE

The IDT71V65703/5903 have an on-chip burst counter. In the burst

The IDT71V65703/5903 SRAMs utilize IDT’s latest high-performance

Supply

Input

I/O

, CE

IDT71V65703

IDT71V65903

, CE

Asynchronous

Synchronous

Static

N/A

) that allow the

DSC-5298/03

5298 tbl 01

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