IDT71T75802 Integrated Device Technology, Inc., IDT71T75802 Datasheet
IDT71T75802
Specifications of IDT71T75802
Available stocks
Related parts for IDT71T75802
IDT71T75802 Summary of contents
Page 1
... There are three chip enable pins (CE user to deselect the device when desired. If any one of these three is not asserted when ADV/LD is low, no new memory operation can be initiated. 1 IDT71T75602 IDT71T75802 Zero , that allow the 1 ...
Page 2
... IDT71T75602, IDT71T75802, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs However, any pending data transfers (reads or writes) will be completed. The data bus will tri-state two cycles after the chip is deselected or a write is initiated. The IDT71T75602/802 have an on-chip burst counter. In the burst mode, the IDT71T75602/802 can provide four cycles of data for a single address presented to the SRAM ...
Page 3
... IDT71T75602, IDT71T75802, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs LBO Address A [0:18] CE1, CE2, CE2 R/W CEN ADV/LD BWx Clock OE TMS TDI TCK TRST (optional) LBO Address A [0:19] CE1, CE2, CE2 R/W CEN ...
Page 4
... IDT71T75602, IDT71T75802, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Symbol Parameter Min. V Core Supply Voltage 2.375 DD V I/O Supply Voltage 2.375 DDQ V Ground Input High Voltage - Inputs 1 Input High Voltage - I/O 1 Input Low Voltage -0 ...
Page 5
... IDT71T75602, IDT71T75802, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs 100 DDQ I I DDQ DDQ DDQ NOTES: 1. Pins 14, 16, and 66 do not have to be connected directly to V the input voltage Pins 38, 39 and 43 will be pulled internally to V disable the TAP controller without interfering with normal operation, several settings are possible ...
Page 6
... IDT71T75602, IDT71T75802, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs NOTES: 1. J3, R5, and J5 do not have to be directly connected U2, U3, U4 and U6 will be pulled internally to V are possible. U2, U3, U4 and U6 could be tied to VDD or VSS and U5 should be left unconnected. Or all JTAG inputs(TMS, TDI, and TCK and TRST) U2, U3, U4 and U6 could be left unconnected “ ...
Page 7
... IDT71T75602, IDT71T75802, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs (5) R/ Chip ADV/ Enable L L Select Select Deselect NOTES Don’t Care When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle ...
Page 8
... IDT71T75602, IDT71T75802, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs First Address Second Address Third Address (1) Fourth Address NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting. ...
Page 9
... IDT71T75602, IDT71T75802, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Cycle Address R/ ADV NOTES defined and High Low Don’t Care High Impedance. Cycle Address ...
Page 10
... IDT71T75602, IDT71T75802, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Cycle Address R/ ADV NOTES High Low Don’t Care High Impedance defined and Cycle Address R/ ADV n n NOTES High Low Don’t Care High Impedance. ...
Page 11
... IDT71T75602, IDT71T75802, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Cycle Address R/ ADV NOTES High Low Don’t Care High Impedance defined and Cycle Address R/ ADV NOTES High Low Don’t Care High Impedance. ...
Page 12
... IDT71T75602, IDT71T75802, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Cycle Address R/ ADV NOTES High Low Don’t Care Don’t Know High Impedance defined and Device Outputs are ensured High-Z after the first rising edge of clock upon power-up. ...
Page 13
... IDT71T75602, IDT71T75802, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Symbol Parameter |I | Input Leakage Current LI , JTAG and ZZ Input Leakage Current | Output Leakage Current LO V Output Low Voltage OL V Output High Voltage OH NOTE: 1. The LBO, TMS, TDI, TCK and TRST pins will be internally pulled to V ...
Page 14
... IDT71T75602, IDT71T75802, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Symbol Parameter t Clock Cycle Time CYC (1) Clock Frequency t F (2) t Clock High Pulse Width CH (2) Clock Low Pulse Width t CL Output Parameters t Clock High to Valid Data ...
Page 15
... IDT71T75602, IDT71T75802, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges 6. ...
Page 16
... IDT71T75602, IDT71T75802, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges 6. ...
Page 17
... IDT71T75602, IDT71T75802, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges 6. ...
Page 18
... IDT71T75602, IDT71T75802, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs CEN Commercial and Industrial Temperature Ranges 6. ...
Page 19
... IDT71T75602, IDT71T75802, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs CS Commercial and Industrial Temperature Ranges 6. ...
Page 20
... IDT71T75602, IDT71T75802, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs t JF TCK (1) Device Inputs / TDI/TMS (2) Device Outputs / TDO ( 3) TRST t JRST NOTES: 1. Device inputs = All device inputs except TDI, TMS and TRST. 2. Device outputs = All device outputs except TDO. ...
Page 21
... IDT71T75602, IDT71T75802, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Instruction Field Revision Number (31:28) IDT Device ID (27:12) IDT JEDEC ID (11:1) ID Register Indicator Bit (Bit 0) Instruction EXTEST SAMPLE/PRELOAD DEVICE_ID HIGHZ RESERVED RESERVED RESERVED RESERVED ...
Page 22
... IDT71T75602, IDT71T75802, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges 6.42 22 ...
Page 23
... IDT71T75602, IDT71T75802, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges 6.42 23 ...
Page 24
... IDT71T75602, IDT71T75802, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs OE OE DATA OUT NOTE read operation is assumed progress. IDT XXXX S XX Device Power Speed Type t OHZ XX X Package Blank 225 200 166 150 133 ...
Page 25
... IDT71T75602, IDT71T75802, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Rev Date Pages 0 04/20/00 1 05/25/00 Pg.1,14,15,25 Pg. 1,2,14 Pg. 23 Pg 08/23/01 Pg. 1,2,24 Pg 10/16/01 Pg. 6 10/29/01 Pg 12/21/01 Pg. 4-6 Pg 06/07/02 Pg. 1-3,6,13,20,21 Added complete JTAG functionality. Pg. 2,13 Pg ...