IDT7025L Integrated Device Technology, IDT7025L Datasheet

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IDT7025L

Manufacturer Part Number
IDT7025L
Description
8k X 16 Dual-port Ram
Manufacturer
Integrated Device Technology
Datasheet

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Features
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Functional Block Diagram
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull.
©2001 Integrated Device Technology, Inc.
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Military: 20/25/35/55/70ns (max.)
– Industrial: 55ns (max.)
– Commercial: 15/17/20/25/35/55ns (max.)
Low-power operation
– IDT7025S
– IDT7025L
Separate upper-byte and lower-byte control for multiplexed
bus compatibility
Active: 750mW (typ.)
Standby: 5mW (typ.)
Active: 750mW (typ.)
Standby: 1mW (typ.)
I/O
I/O
8L
0L
BUSY
-I/O
-I/O
SEM
R/W
A
INT
UB
CE
OE
LB
A
12L
15L
0L
7L
L
L
L
L
L
L
L
L
(1,2)
(2)
Decoder
Address
R/W
OE
CE
L
L
L
HIGH-SPEED
8K x 16 DUAL-PORT
STATIC RAM
13
Control
I/O
ARBITRATION
SEMAPHORE
INTERRUPT
MEMORY
ARRAY
LOGIC
M/S
1
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IDT7025 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
M/S = H for BUSY output flag on Master
M/S = L for BUSY input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Battery backup operation—2V data retention
TTL-compatible, single 5V (±10%) power supply
Available in 84-pin PGA, Flatpack, PLCC, and 100-pin Thin
Quad Flatpack
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Control
I/O
13
Decoder
Address
CE
OE
R/W
R
R
R
NOVEMBER 2001
2683 drw 01
IDT7025S/L
R/W
LB
CE
OE
I/O
I/O
BUSY
A
A
SEM
UB
INT
12R
0R
R
8R
0R
R
R
R
R
R
R
(2)
-I/O
-I/O
R
(1,2)
15R
7R
DSC 2683/9

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IDT7025L Summary of contents

Page 1

... Commercial: 15/17/20/25/35/55ns (max.) ◆ ◆ ◆ ◆ ◆ Low-power operation – IDT7025S Active: 750mW (typ.) Standby: 5mW (typ.) – IDT7025L Active: 750mW (typ.) Standby: 1mW (typ.) ◆ ◆ ◆ ◆ ◆ Separate upper-byte and lower-byte control for multiplexed bus compatibility ...

Page 2

IDT7025S/L High-Speed Dual-Port Static RAM Description The IDT7025 is a high-speed Dual-Port Static RAM. The IDT7025 is designed to be used as a stand-alone 128K-bit Dual-Port RAM combination MASTER/SLAVE Dual-Port RAM ...

Page 3

IDT7025S/L High-Speed Dual-Port Static RAM Pin Configurations I/O 10L 67 09 I/O 11L 69 08 I/O 13L 72 07 I/O 15L ...

Page 4

IDT7025S/L High-Speed Dual-Port Static RAM Truth Table I: Non-Contention Read/Write Control (1) Inputs R ...

Page 5

IDT7025S/L High-Speed Dual-Port Static RAM Absolute Maximum Ratings Symbol Rating Commercial & Industrial (2) V Terminal Voltage -0.5 to +7.0 TERM with Respect to GND T Temperature -55 to +125 BIAS Under Bias T Storage -65 to ...

Page 6

IDT7025S/L High-Speed Dual-Port Static RAM DC Electrical Characteristics Over the 0perating Temperature and Supply Voltage Range Symbol Parameter Test Condition Dynamic Operating CC , Outputs Disabled IL Current SEM = V IH (Both ...

Page 7

IDT7025S/L High-Speed Dual-Port Static RAM Data Retention Characteristics Over All Temperature Ranges (L Version Only) Symbol Parameter V V for Data Retention Data Retention Current CCDR (3) t Chip Dese lect to Data Retention ...

Page 8

IDT7025S/L High-Speed Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter READ CYCLE t Read Cycle Time RC t Address Access Time AA t (3) Chip Enable Access Time ACE ...

Page 9

IDT7025S/L High-Speed Dual-Port Static RAM Waveform of Read Cycles ADDR CE OE UB, LB R/W DATA OUT BUSY OUT NOTES: 1. Timing depends on which signal is asserted last, OE, CE, LB, or UB. 2. Timing depends ...

Page 10

IDT7025S/L High-Speed Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Symbol Parameter WRITE CYCLE t Write Cycle Time WC (3) t Chip Enable to End-of-Write EW t Address Valid to End-of-Write AW ...

Page 11

IDT7025S/L High-Speed Dual-Port Static RAM Timing Waveform of Write Cycle No. 1, R/W Controlled Timing ADDRESS OE ( SEM ( ( R/W (4) DATA OUT DATA IN Timing Waveform of ...

Page 12

IDT7025S/L High-Speed Dual-Port Static RAM Timing Waveform of Semaphore Read after Write Timing, Either Side VALID ADDRESS t AW SEM DATA R/W OE Write Cycle NOTE ...

Page 13

IDT7025S/L High-Speed Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature Supply Voltage Range Symbol Parameter BUSY TIMING (M BUSY Access Time from Address Match t BAA BUSY Disable Time from Address ...

Page 14

IDT7025S/L High-Speed Dual-Port Static RAM Timing Waveform of Write Port-to-Port Read and BUSY ADDR "A" R/W "A" DATA IN "A" (1) t APS ADDR "B" BUSY "B" DATA OUT "B" NOTES ensure that the earlier ...

Page 15

IDT7025S/L High-Speed Dual-Port Static RAM Waveform of BUSY Arbitration Controlled by CE Timing ADDR "A" and "B" CE "A" (2) t APS CE "B" BUSY "B" Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing (M/S ...

Page 16

IDT7025S/L High-Speed Dual-Port Static RAM Waveform of Interrupt Timing ADDR "A" ( "A" R/W "A" INT "B" ADDR "B" "B" OE "B" INT "B" NOTES: 1. All timing is the same ...

Page 17

IDT7025S/L High-Speed Dual-Port Static RAM Truth Table II — Address BUSY Arbitration Inputs Outputs 12L CE CE BUSY ( 12R MATCH MATCH ...

Page 18

IDT7025S/L High-Speed Dual-Port Static RAM Busy Logic Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to ...

Page 19

IDT7025S/L High-Speed Dual-Port Static RAM that semaphore’s status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. Once the ...

Page 20

IDT7025S/L High-Speed Dual-Port Static RAM variable, depending upon the complexity of the software using the semaphore flags. All eight semaphores could be used to divide the Dual- Port RAM or other shared resources into eight parts. Semaphores ...

Page 21

... Pages 5,6,8,10,13&15 Removed Industrial temp footnote from all tables Page 21 Added Industrial temp to 20ns in ordering information CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 The IDT logo is a registered trademark of Integrated Device Technology, Inc. Military, Industrial and Commercial Temperature Ranges A A Process/ ...

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