IDT7009 Integrated Device Technology, IDT7009 Datasheet
IDT7009
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IDT7009 Summary of contents
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... Low-power operation – IDT7009L Active: 1W (typ.) Standby: 1mW (typ.) ◆ Dual chip enables allow for depth expansion without external logic ◆ IDT7009 easily expands data bus width to 16 bits or more using the Master/Slave select when cascading more Functional Block Diagram R ...
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... IDT7009L High-Speed 128K x 8 Dual-Port Static RAM Description The IDT7009 is a high-speed 128K x 8 Dual-Port Static RAM. The IDT7009 is designed to be used as a stand-alone 1024K-bit Dual-Port RAM combination MASTER/SLAVE Dual-Port RAM for 16-bit-or- more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-bit or wider memory system applications results in full- speed, error-free operation without the need for additional discrete logic ...
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... IDT7009L High-Speed 128K x 8 Dual-Port Static RAM Pin Names Left Port Right Port CE CE Chip Enables , R/W R/W Read/Write Enable Output Enable Address 0L 16L 0R 16R I/O - I/O I/O - I/O Data Input/Output SEM SEM Semaphore Enable L R INT ...
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... IDT7009L High-Speed 128K x 8 Dual-Port Static RAM Truth Table I: Chip Enable < 0.2V >V -0. >V -0. <0.2V NOTES: 1. Chip Enable references are shown above with the actual and ' CMOS standby requires ' either < 0.2V or > V ...
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... IDT7009L High-Speed 128K x 8 Dual-Port Static RAM DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter ( Input Leakage Current LI |I Output Leakage Current | LO V Output Low Voltage OL V Output High Voltage OH NOTES Vcc < 2.0V, input leakages are undefined. ...
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... IDT7009L High-Speed 128K x 8 Dual-Port Static RAM AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load Waveform of Read Cycles ADDR ( R/W DATA OUT BUSY OUT Timing of Power-Up Power-Down ( NOTES: 1. Timing depends on which signal is asserted last CE. ...
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... IDT7009L High-Speed 128K x 8 Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol READ CYCLE t Read Cycle Time RC t Address Access Time AA (4) t Chip Enable Access Time ACE t Output Enable Access Time AOE t Output Hold from Address Change ...
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... IDT7009L High-Speed 128K x 8 Dual-Port Static RAM Timing Waveform of Write Cycle No. 1, R/W Controlled Timing ADDRESS OE (9,10 SEM ( R/W DATA (4) OUT DATA IN Timing Waveform of Write Cycle No Controlled Timing ADDRESS (9,10 SEM ( R/W DATA IN NOTES during all address transitions write occurs during the overlap (t ...
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... IDT7009L High-Speed 128K x 8 Dual-Port Static RAM Timing Waveform of Semaphore Read after Write Timing, Either Side VALID ADDRESS SEM DATA R/W OE NOTES for the duration of the above timing (both write and read cycle) (Refer to Chip Enable Truth Table). ...
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... IDT7009L High-Speed 128K x 8 Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol BUSY TIMING (M/S BUSY Access Time from Address Match t BAA BUSY Disable Time from Address Not Matched t BDA BUSY Access Time from Chip Enable Low ...
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... IDT7009L High-Speed 128K x 8 Dual-Port Static RAM Timing Waveform of Write with Port-to-Port Read and BUSY (M ADDR "A" R/W "A" DATA IN "A" (1) t APS ADDR "B" BUSY "B" DATA OUT "B" NOTES ensure that the earlier of the two ports wins ...
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... IDT7009L High-Speed 128K x 8 Dual-Port Static RAM Waveform of BUSY Arbitration Controlled by CE Timing (M ADDR "A" and "B" CE "A" (2) t APS CE "B" BUSY "B" Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing (M (1) IH ADDR "A" ADDR " ...
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... IDT7009L High-Speed 128K x 8 Dual-Port Static RAM Waveform of Interrupt Timing ADDR "A" "A" R/W "A" INT "B" ADDR "B" CE "B" OE "B" INT "B" NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”. ...
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... NOTES: 1. Pins BUSY and BUSY are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT7009 are L R push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes. 2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address is not met, either BUSY and enable inputs of this port ...
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... BUSY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the BUSY signal as a write inhibit signal. Thus on the IDT7009 RAM the BUSY pin is an output if the part is used as a master (M/S pin = V the BUSY pin is an input if the part used as a slave (M/S pin = V in Figure 3 ...
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... The eight semaphore flags reside within the IDT7009 in a separate memory space from the Dual-Port RAM. This address space is accessed by placing a LOW input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, CE, and R/W) as they would be used in accessing a standard Static RAM ...
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... IDT7009L High-Speed 128K x 8 Dual-Port Static RAM Ordering Information IDT XXXXX A 999 A Device Power Speed Package Type NOTE: 1. Contact your local sales office for industrial temp range for other speeds, packages and powers. Datasheet Document History 09/30/99: 11/10/99: 01/05/01: Page 3 Page 5 Page 14 01/24/02: Page 2 Pages & 12 Pages & ...