ICS83905AGI ICST [Integrated Circuit Systems], ICS83905AGI Datasheet

ICS83905AGI

Manufacturer Part Number

ICS83905AGI

Description

LOW SKEW, 1:6 CRYSTAL INTERFACE-TO LVCMOS/LVTTL FANOUT BUFFER

Manufacturer

ICST [Integrated Circuit Systems]

Datasheet

1.ICS83905AGI.pdf (16 pages)

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50W series or parallel terminated transmission lines. The ef-

fective fanout can be increased from 6 to 12 by utilizing the

ability of the outputs to drive two series terminated lines.

The ICS83905I is characterized at full 3.3V, 2.5V, and 1.8V,

mixed 3.3V/2.5V, 3.3V/1.8V and 2.5V/1.8V output operating

supply mode. Guaranteed output and part-to-part skew

characteristics along with the 1.8V output capabilities makes

the ICS83905I ideal for high performance, single ended appli-

cations that also require a limited output voltage.

83905AGI

XTAL_OUT

ENABLE 1

ENABLE 2

HiPerClockS™

ICS

XTAL_IN

ENERAL

LOCK

The ICS83905I is a low skew, 1-to-6 LVCMOS /

LVTTL Fanout Buffer and a member of the

HiPerClockS™ family of High Performance Clock

Solutions from ICS. The low impedance

LVCMOS/LVTTL outputs are designed to drive

IAGRAM

Integrated

Circuit

Systems, Inc.

SYNCHRONIZE

ESCRIPTION

http://www.icst.com/products/hiperclocks.html

BCLK0

BCLK1

BCLK2

BCLK3

BCLK4

BCLK5

6 LVCMOS / LVTTL outputs

Outputs able to drive 12 series terminated lines

Crystal oscillator interface

Crystal input frequency range: 10MHz to 40MHz

Output skew: 80ps (maximum)

RMS phase jitter @ 25MHz, (100Hz - 1MHz):

0.26ps (typical) (V

Phase noise:

5V tolerant enable inputs

Synchronous output enables

Operating power supply modes:

Full 3.3V, 2.5V and 1.8V,

mixed 3.3V core/2.5V output operating supply,

mixed 3.3V core/1.8V output operating supply,

mixed 2.5V core/1.8V output operating supply

-40°C to 85°C ambient operating temperature

Lead-Free package fully RoHS compliant

100kHz .............. -157.3 dBc/Hz

EATURES

Offset

100Hz .............. -129.7 dBc/Hz

10kHz .............. -147.3 dBc/Hz

1kHz .............. -144.4 dBc/Hz

LVCMOS / LVTTL F

SSIGNMENT

KEW

4.4mm x 5.0mm x 0.92mm body package

, 1:6 C

Noise Power

= V

XTAL_OUT

DDO

ENABLE 2

BCLK0

BCLK1

BCLK2

= 2.5V)

GND

RYSTAL

16-Lead TSSOP

ICS83905I

G Pacakge

Top View

ICS83905I

ANOUT

NTERFACE

REV. B MAY 16, 2005

XTAL_IN

ENABLE 1

BCLK5

BCLK4

GND

BCLK3

DDO

UFFER

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ICS83905AGI Summary of contents

Page 1

Integrated Circuit Systems, Inc ENERAL ESCRIPTION The ICS83905I is a low skew, 1-to-6 LVCMOS / ICS LVTTL Fanout Buffer and a member of the HiPerClockS™ HiPerClockS™ family of High Performance Clock Solutions from ICS. The low impedance LVCMOS/LVTTL ...

Page 2

Integrated Circuit Systems, Inc ABLE IN ESCRIPTIONS ...

Page 3

Integrated Circuit Systems, Inc BSOLUTE AXIMUM ATINGS Supply Voltage Inputs, V -0. Outputs, V -0. Package Thermal Impedance Lead TSSOP package 89°C/W (0 lfpm) Storage Temperature, T ...

Page 4

Integrated Circuit Systems, Inc ABLE OWER UPPLY HARACTERISTICS ...

Page 5

Integrated Circuit Systems, Inc ABLE HARACTERISTICS ...

Page 6

Integrated Circuit Systems, Inc ABLE HARACTERISTICS ...

Page 7

Integrated Circuit Systems, Inc ABLE HARACTERISTICS ...

Page 8

Integrated Circuit Systems, Inc YPICAL HASE 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 YPICAL HASE 0 -10 -20 -30 -40 -50 -60 ...

Page 9

Integrated Circuit Systems, Inc. P ARAMETER 1.65V± DDO LVCMOS GND -1.165V±5% 3.3V /3. CORE UTPUT OAD EST 0.9V±0. DDO LVCMOS GND -0.9V ± 0.1V 1.8V C /1.8V O ...

Page 10

Integrated Circuit Systems, Inc. V DDO DDO Qy 2 tsk( UTPUT KEW 80% 20% Clock t Outputs UTPUT ISE ALL IME 83905AGI KEW LVCMOS / LVTTL F ...

Page 11

Integrated Circuit Systems, Inc RYSTAL NPUT NTERFACE Figure 1A shows an example of ICS83905I crystal interface with a parallel resonant crystal. The frequency accuracy can be fine tuned by adjusting the C1 and C2 values. For a ...

Page 12

Integrated Circuit Systems, Inc AYOUT UIDELINE Figure 2 shows an example of ICS83905I application schematic. In this example, the device is operated at V 3.3V. The decoupling capacitors should be located as close as possible to the power ...

Page 13

Integrated Circuit Systems, Inc ABLE VS IR LOW ABLE FOR JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in ...

Page 14

Integrated Circuit Systems, Inc ACKAGE UTLINE UFFIX FOR T ABLE Reference Document: JEDEC Publication 95, MO-153 83905AGI LVCMOS / LVTTL F TSSOP EAD TSSOP ACKAGE IMENSIONS FOR ...

Page 15

Integrated Circuit Systems, Inc ABLE RDERING NFORMATION ...

Page 16

Integrated Circuit Systems, Inc ...

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